Telephone terminal and telephone exchange system accommodating the terminal

A telephone exchange system comprising:

• an exchanger having a trunk connected to public lines;
• a digital telephone terminal line circuit connected to a telephone terminal;
• a speech path switch for changing and connecting the trunk and the digital telephone terminal line circuit;
• and
• a central controller for controlling exchange connection operations of the speech path switch,
• wherein the telephone terminal includes,
• a display;
• a first controller for controlling the display;
• a line control means for executing an interfacing operation with the display;
• a detection means for detecting operational selection of information concerning speech controls displayed on the display;
• a second controller for controlling the line control means and the detection means;
• and
• a common memory having a first port accessible to the first controller and a second port accessible to the second controller,
• wherein the second controller includes,
• means for sending display instruction information corresponding to the selection information to the first controller through the common memory when the selection information corresponding to an operative selection issued from the detection means is received by the second controller;
• and
• means for sending speech control information to the line control means.

A telephone terminal comprising:

• a display;
• a first controller having a first microprocessor for controlling the display;
• a line control unit that executes an interfacing operation with the display;
• a detection unit that detects operation selection of information concerning speech controls displayed on the display;
• a second controller having a second microprocessor for controlling the line control unit and the detection unit;
• and
• a common memory having a first port accessible to the first controller and a second port accessible to the second controller,
• wherein both the first and second controllers periodically carry out an access to the common memory based on interrupt signals received at respective interrupt inputs on the first and second controllers, and
• wherein, when the second controller is not interrupted for at least a fixed period of time, the second controller sends a reset signal to the first controller to reset the first controller so as to remove the first controller from an abnormal state that the first controller is determined to be in.