Decoding of a biphase modulated bitstream and relative self-synchronizing frequency divider with noninteger ratio

A circuit for generating a signal in phase synchronization with a biphase modulated digital input signal, the circuit comprising:

• a first detection circuit comprising
• a clock input for receiving a master clock signal having a frequency higher than a maximum frequency of the biphase modulated digital input signal, and
• an input for receiving the biphase modulated digital input signal, said first detection circuit generating a first control signal responsive to detection of at least one first predetermined sampled value of the biphase modulated digital input signal with the master clock signal;
• a second detection circuit comprising
• a clock input for receiving the master clock signal, and
• an input for receiving the biphase modulated digital input signal, said second detection circuit generating a second control signal responsive to detection of at least one second predetermined sampled value of the biphase modulated digital input signal with the master clock signal;
• and a controlled frequency divider comprising
• an output for providing the phase synchronized signal based upon the master clock signal,
• a clock input for receiving the master clock signal,
• a first input for receiving the first control signal for enabling or disabling switching of the output, and
• a second input for receiving the second control signal for enabling or disabling switching of the output.

A method of decoding a biphase modulated digital input signal, the method comprising:

• dividing a frequency of a master clock signal according to a non-integer ratio using a frequency divider circuit having a predetermined integer number, the dividing comprising
• sampling the biphase modulated digital input signal with the master clock signal using a first detection circuit, and analyzing at least one sampled value,
• sampling the biphase modulated digital input signal with the master clock signal using a second detection circuit, and analyzing at the least one sampled value,
• generating a first control signal based upon detection by the first detection circuit of at least one first predetermined sampled value,
• generating a second control signal based upon detection by the second detection circuit of at least one second predetermined sampled value, and
• enabling or disabling switching of the frequency divider circuit responsive to the first and second control signals;
• generating a sampling signal that is self-synchronized with the biphase modulated digital input signal, and being derived from the master clock signal having a frequency multiple of a maximum frequency of the biphase modulated digital input signal;
• and
• sampling the biphase modulated digital input signal with the sampling signal that is in phase synchronization with the biphase modulated digital input signal.

A digital circuit for decoding a biphase modulated digital input signal, the digital circuit comprising:

• a frequency divider circuit for generating a sampling signal that is self-synchronized with the biphase modulated digital input signal, the sampling signal being derived by division by a non-integer of a master clock signal, the master clock signal having a frequency multiple of a maximum frequency of the biphase modulated digital input signal;
• a first detection circuit for sampling the biphase modulated digital input signal with the master clock signal, analyzing at least one sampled value, and generating a first control signal based upon detection by said first detection circuit of at least one first predetermined sampled value;
• a second detection circuit for sampling the biphase modulated digital input signal with the master clock signal, analyzing the at least one sampled value, and generating a second control signal based upon detection by said second detection circuit of at least one second predetermined sampled value;
• switching of said frequency divider circuit being enabled or disabled based upon the first and second control signals;
• and
• a sampling circuit for sampling the biphase modulated digital input signal with the sampling signal that is in phase synchronization with the biphase modulated digital input signal.