Method and apparatus for programmable pulse width modulated signal generation with period and duty cycle values updated with controlled relative timing

An apparatus including a pulse width modulation (PWM) timing circuit for generating a signal having a programmable period and a programmable duty cycle, comprising:

• a storage element configured to store at least a period value and a duty cycle value;
• a counter configured to receive a clock signal and in accordance therewith generate a count value;
• a comparison circuit, coupled to said storage element and said counter, said comparison circuit configured to compare said count value, said period value, and said duty cycle value, and in accordance therewith generate a period match signal and an output signal;
• and
• an update sequencer circuit, coupled to said storage element and said comparison circuit, said update sequencer circuit configured to detect an updated period value and an updated duty cycle value, and to receive said period match signal, and in accordance therewith selectively generate a period write signal and a duty cycle write signal,
• wherein said storage element is further configured to receive said updated period value, said updated duty cycle value, said period write signal, and said duty cycle write signal, and in accordance therewith replace said period value with said updated period value and said duty cycle value with said updated duty cycle value.