Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology
AssigneeMicron Technology, Inc.
InventorMark R. Thomann
Life of this patent
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Abstract
An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
Claims33
A data switch comprising;
- Y input serial access memories each for receiving an input data package of a predetermined length X;
- a dynamic random access memory array;
- Y output serial access memories each for storing an output data package of a predetermined length X;
- data transfer buses for transferring input data packages from the Y input serial access memories to the dynamic random access memory array, the data transfer buses further transferring the input data packages from the dynamic random access memory array to the Y output serial access memories;
- an input edit buffer for editing the input data package prior to transferring to the dynamic random access memory;
- an output edit buffer for editing the input data package prior to transferring to the Y output serial access memories;
- and
- a controller for configuring the Y input and output serial access memories to store a portion of the full data package of length X, such that an X length data package can be serially input or output from the Y input and output serial access memories in X/Y clock cycles.
A communication system comprising:
- a processor;
- data communication bus lines coupled to the processor;
- and
- an asynchronous transfer mode (ATM) switch coupled to the data communication bus lines and comprising:
- a dynamic random access memory array;
- double buffered input serial access memories each for receiving an ATM data package;
- double-buffered output serial access memories each for storing an ATM data package;
- an edit circuit for modifying an ATM data package;
- and
- control circuitry.
A method of operating a multiport memory comprising a random access memory (RAM) array and Y input double buffered serial access memories, each double buffered serial access memory having a maximum storage capacity of a full data package having a length of X bits, the method comprising:
- selecting a data width mode using a controller of the multiport memory;
- configuring the Y double buffered serial access memories so that each double buffered serial access memory stores a portion of a full data package;
- and
- serially inputting an X bit data package into the Y double buffered serial access memories in X/Y clock cycles;
- editing the X bit data package prior to transferring the X bit data package to the RAM;
- and
- transferring the X bit data package from the double buffered serial access memories to the RAM simultaneously.
A method of operating a multiport memory comprising a random access memory (RAM) array and N input double buffered serial access memories, each double buffered serial access memory having a maximum storage capacity of a full data package, the method comprising:
- selecting a data width mode using a controller of the multiport memory;
- configuring the N SAMs so that each input double buffered serial access memory stores 1/N of the full data package;
- editing the X bit data package prior to transferring the X bit data package to the RAM;
- and
- transferring the full data package from the N input double buffered serial access memories to the RAM on one clock signal.
A method of operating a communication system comprising:
- transmitting a data package comprising X bits from a processor to an ATM switch via a data bus;
- receiving the X bits with the ATM switch;
- storing the X bits in input buffers of the ATM switch;
- transferring the X bits from the input buffers to a plurality of input serial access memories;
- editing the X bit data package prior to transferring the X bit data package to the RAM;
- and
- transferring the X bits from the input serial access memories to a random access memory array.
Dependencies are inferred from the claim text.