Synchronous dynamic random access memory
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
A synchronous memory includes a memory cell array with a plurality of memory cells arranged in a matrix, the memory cell array being divided into four banks respectively including a plurality of memory cell arrays therein, the synchronous memory further including a first bus for transferring data from and to the memory cell arrays in the first and the second banks, a second bus for transferring data from and to the memory cell arrays in the third and the fourth banks, and an activating circuit for selectively activating memory cell arrays belong to a single bank of the first to fourth banks so that at least two memory cell arrays within the single bank are simultaneously activated.
Claims22
A synchronous memory, comprising:
- a plurality of memory cells arranged in a matrix, the memory cells being divided into first, second, third and fourth banks arranged in a first direction, each of the banks having a plurality of memory cell arrays arranged in a second direction;
- a first I/O bus arranged between the first and the second banks for transferring data from and to the mernory cell arrays in the first and the second banks;
- a second I/O bus arranged between the third and the fourth banks for transferring data from and to the memory cell arrays in the third and the fourth banks;
- and
- an activating circuit for selectively activating memory cell arrays belonging to a single bank of the first to fourth banks so that at least two memory cell arrays within the single bank are simultaneously activated.
Dependencies are inferred from the claim text.