Memory row line driver circuit

Abstract

A line driver circuit is disclosed which may comprise a first supply voltage potential node; a second supply voltage potential node; a latch node; a first transistor of a first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the latch node, and a gate; a second transistor of the first conductivity type and having a source coupled to the first supply voltage potential node, a drain coupled to the gate of the first transistor of the first conductivity type, and a gate coupled to the latch node; a first transistor of a second conductivity type opposite to the first conductivity type and having a drain coupled to the drain of the second transistor of the first conductivity type, a source coupled to the second supply voltage potential node and a gate coupled to the latch node; and a diode having an anode coupled to the input node and a cathode coupled to the second supply voltage potential node.

Dependencies are inferred from the claim text.