Semiconductor memory

A semiconductor memory, in which a memory array comprising a plurality of bit line pairs driven by a signal based on data, a plurality of word lines driven by a signal based on an address, and memory cells placed on intersections thereof is supplied with a signal based on said data and said address, and said plurality of bit line pairs and said plurality of word lines are driven so that said data is written into said memory cells via said plurality of bit line pairs, said semiconductor memory comprising:

• a plurality of level shifters for producing a first select signal, which vary in voltage level between a first source voltage and a ground in response to a first address signal, and are activated at a ground level to select one of said word lines;
• and
• a plurality of word drivers for driving a selected one of said plurality of word lines in response to said first select signal;
• each of said word drivers comprising:
• a first transistor of a first conductivity type inserted between an associated word line and a power line for supplying said first source voltage;
• and
• a second transistor of a second conductivity type inserted between said associated word line and the ground,
• said first select signal being inputted to a gate of said first transistor via a switch controlled by a second address signal different from said first address signal, and being inputted to a gate of said second transistor.