Semiconductor memory device with reduced current consumption in data hold mode

#1. Field of the Invention

#The present invention relates generally to semiconductor devices, and in particular to configurations for reducing the current consumed in a refresh mode for holding data, such as a sleep mode or a power down mode, without causing an erroneous operation in a semiconductor memory device requiring refreshing of storage data. More specifically, the present invention relates to a configuration for reducing the current consumed in a refresh mode by a logic merged memory with a logic and a dynamic random access memory integrated on a single semiconductor chip.

#2. Description of the Background Art

#FIG. 1 schematically shows an entire configuration of a semiconductor device according to the present invention.

#FIG. 2 schematically shows a configuration of a semiconductor device according to a first embodiment of the present invention.

#FIG. 3 schematically shows a configuration of a power supply circuit for the column-related/peripheral control circuitry shown in FIG. 2.

#First Embodiment

#FIG. 1 schematically shows an entire configuration of a semiconductor device with the present invention applied thereto. In FIG. 1, a semiconductor device 10 according to the present invention includes a DRAM macro 11 including 1 transistor-1 capacitor type dynamic memory cells, and a logic circuit 12 transmitting and receiving data to and from DRAM macro 11. DRAM macro 11 and logic circuit 12 are integrated on a single semiconductor clip.

#DRAM macro 11 includes a DRAM cell array 13 having dynamic memory cells, and DRAM peripheral circuitry 14 basically for selecting a memory cell included in DRAM cell array 13 and for reading/writing data.