US 6,487,135 B2Granted

Semiconductor device

AssigneeHitachi, Ltd.

InventorsTakao Watanabe, Hiroyuki Mizuno, Satoru Akiyama

Life of this patent

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Abstract

A memory includes firs circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bLs coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cell in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.

Claims13

Dependent claims

A semiconductor device, comprising:

a first circuit including a plurality of memory cells, said first circuit operating in response to a first clock signal;
a second circuit and a third circuit which are coupled with said first circuit;
and
a bus for coupling said first circuit to said second and third circuits, wherein:
said second circuit outputs, in response to a second clock signal, a first a dress signal to said first circuit;
said third circuit outputs, in response to a third clock signal, a second address signal to said first circuit;
said first circuit includes a refresh control circuit for executing a refresh operation for the memory cells in response to a fourth clock signal and an address latch for storing said first or second address signal in response to said first clock signal;
and
said first clock signal has a frequency equal to or more than a sum of frequencies respectively of said second, third, and fourth clock signals.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/931,895Filed 20 Aug 2001
Priority: JP 2000-33724031 Oct 2000
Published: US 2002/0051397 A12 May 2002
Granted: 26 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles