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AssigneeBAE Systems Information and Electronic Systems Integration Inc.
InventorsNandor G. Thoma, Scott E. Doyle
Estimating the term…
A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
A single-event upset tolerant sense latch circuit, comprising:
A memory device, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Term ended 9 Aug 2021 (estimated)
1. Technical Field
The present invention relates to integrated circuits in general, and in particular to bi-stable integrated circuits. Still more particularly, the present invention relates to a single-event upset tolerant latch for sense amplifiers.
2. Description of the Prior Art
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic diagram of a conventional sense latch;
FIG. 2 is a schematic diagram of a conventional inverter;
With reference now to FIG. 2, there is illustrated a schematic diagram of an inverter. As shown, an inverter 20 includes a p-channel transistor 21 connected in series with an n-channel transistor 22. The source of p-channel transistor 21 is connected to a power supply, and the source of n-channel transistor 22 is connected to ground. P-channel transistor 21 conducts when its gate potential is more negative than its threshold voltage, and n-channel transistor 22 conducts when its gate potential is more positive than its threshold voltage.
The input-output characteristics of inverter 20 can be graphically illustrated, as shown in FIG. 3. The Y-axis of a graph 30 plots input signal amplitudes, and the X-axis of graph 30 plots time. An input voltage Vin to inverter 20 is plotted as a linear ramp. As input voltage Vin crosses a threshold voltage 31 of n-channel transistor 22, an output voltage Vout from inverter 20 begins to decrease, eventually equaling input voltage Vin at an unity gain point 32. As input voltage Vin continues to increase, output voltage Vout continues to decrease until input voltage Vin arrives at a threshold voltage 33 of p-channel transistor 21, at which point p-channel transistor 21 stops conducting for all effective purposes. The voltage at unity gain point 32 is established by the relative current gains of both p-channel transistor 21 and n-channel transistor 22. For equal positive and negative transition times, unity gain point 32 is at half of the supply voltage value (Vdd) to inverter 20. From a radiation hardening viewpoint, unity gain point 32 is also the optimum point because the noise transients will not be stretched in width, and there is equal balance for noise pulses on the power and ground distributions.
Thus, if input noise pulses to inverter 20 are below the absolute value of the threshold voltages of the two transistors within inverter 20, noise pulses do not propagate through inverter 20, as shown by triangular pulses 34 and 35 to the left of graph 30. This allows reliable operation in a very noisy environment.