Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations

A method of writing data to an integrated circuit memory device, comprising the steps of:

• providing a memory cell array that comprises a plurality of memory cells;
• writing data to the memory cell array over a first input/output bus;
• writing data to the memory cell array over a second input/output bus;
• and
• driving the first and second input/output buses to a predetermined voltage level between the steps of writing data to the memory cell array over the first input/output bus and writing data to the memory cell array over the second input/output bus.

An integrated circuit memory device, comprising:

• a memory cell array that comprises a plurality of memory cells;
• means for writing data to the memory cell array over a first input/output bus;
• means for driving the first and second input/output buses to a predetermined level, responsive to the means for writing data to the memory cell array over the first input/output bus;
• and
• means for writing data to the memory cell array over a second input/output bus, responsive to the means for driving.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells, a plurality of word lines and a plurality of bit line pairs;
• first and second input/output buses arranged at both sides of the memory cell array, respectively;
• a plurality of column selection lines each for simultaneously selecting the first and second input/output buses;
• a precharge circuit for charging the first and second input/output buses at a predetermined voltage in response to a precharge signal during a full-page mode;
• and
• a precharge controller for generating the precharge signal during the full-page mode, wherein the precharge controller generates the precharge signal of a pulse form between a first period, in which data is written to the array via the first input/output bus at an (n−1)th cycle of a clock signal, and a second period, in which data is written to the array via the second input/output bus at an n-th cycle of the clock signal.

A synchronous semiconductor memory device having a full-page mode in which all memory cells in a row are accessed, comprising:

• a memory cell array of memory cells arranged in plural rows and plural columns;
• a first plurality of input/output line pairs arranged at a first side of the memory cell array;
• a second plurality of input/output line pairs arranged at a second side of the memory cell array;
• a plurality of column selection lines each for simultaneously activating the input/output line pairs of the first and second pluralities;
• a plurality of precharge transistors coupled to the input/output line pairs of the first and second pluralities, for charging the input/output line pairs of the first and second pluralities at a predetermined voltage in response to a precharge signal during the full-page mode;
• a precharge controller for generating the precharge signal of a pulse form during the full-page mode;
• and
• driving means including a first driving circuit, which supplies the input/output line pairs of the first plurality with data to be written to the memory cell array, and a second driving circuit, which supplies the input/output line pairs of the second plurality with data to be written to the memory cell array;
• wherein the precharge controller generates the precharge signal of the pulse form after data is written to the array via the first input/output line pairs of the first plurality at an (n−1)th cycle of a clock signal and before data is written to the array via the second input/output line pairs of the second plurality at an n-th cycle of the clock signal.

A method of writing data to a synchronous semiconductor memory device which has a memory cell array of memory cells arranged in plural rows and plural columns, a first plurality of input/output line pairs arranged at one side of the memory cell array, and a second plurality of input/output line pairs arranged at the other side of the memory cell array, the method comprising the steps of:

• writing data to the memory cell array via the first plurality of input/output line pairs;
• checking whether internal column address bit signals all transition to logic “1”
• precharging the first and second pluralities of input/output line pairs at a predetermined voltage when the internal column address bit signals all transition to logic “1”;
• and
• writing data to the memory cell array via the second plurality of input/output line pairs.

An integrated circuit memory device comprising:

• a memory cell array comprising a plurality of memory cells, a plurality of word lines and a plurality of bit line pairs;
• first and second input/output buses arranged at both sides of the memory cell array, respectively;
• a plurality of column selection lines that are configured to select the first and second input/output buses;
• a precharge circuit that is configured to charge the first and second input/output buses at a predetermined voltage in response to a precharge signal during a full-page mode;
• and
• a precharge controller that is configured to generate the precharge signal during the full-page mode between a first time interval in which data is written to the array via the first input/output bus and a second time interval in which data is written to the array via the second input/output bus.