Method and apparatus for testing a CAM addressed cache
AssigneeIntel Corporation
InventorsLawrence T. Clark, Jay B. Miller
Life of this patent
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Abstract
In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
Claims15
An apparatus comprising:
- an array of content addressable memory (CAM) cells, including a first plurality of CAM cells and a second plurality of CAM cells, the second plurality having a width sufficient to address a height of the array;
- and
- a first plurality of CAM drivers are coupled to the array for driving the first plurality of CAM cells, wherein the first plurality of drivers prevent the first plurality of CAM cells from participating in a match in a test mode.
A method comprising:
- disabling a first plurality of content addressable memory (CAM) cells of a CAM array from participating in a match;
- driving a second plurality of CAM cells of the CAM array to participate in the match, the second plurality having a width sufficient to address a height of the CAM array.
A computer readable storage media containing executable computer program instructions which when executed cause a digital processing system to perform a method comprising:
- driving a content addressable memory (CAM) array into a test mode;
- disabling a first plurality of CAM drivers for the CAM array;
- enabling a second plurality of CAM drivers for the CAM array such that only CAM cells driven by the second plurality of CAM drivers can participate in a match.
Dependencies are inferred from the claim text.