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US 6,487,128 B2Granted
Integrated memory having memory cells and reference cells, and operating method for such a memory
AssigneeInfineon Technologies AG
InventorsThomas Böhm, Heinz Hönigschmid, Thomas Röhr, Georg Braun, Zoltan Manyoki
Life of this patent
Estimating the term…
Abstract
The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
Claims10
An integrated memory, comprising:
- a first pair of bit lines;
- a plurality of word lines and reference word lines;
- memory cells respectively arranged at crossing points of said word lines with a bit line of said first pair of bit lines and each having a selection switching element for connecting said memory cell with a respective said bit line and said selection switching element having a control connection connected to a respective said word line;
- a first differential read amplifier connected to said bit lines of said first pair of bit lines and a second differential read amplifier;
- two reference cells respectively arranged at a crossing point of one of said bit lines and a reference word line, having a structure substantially corresponding to a structure of said memory cells, and having a selection switching element for connecting said reference cells via a circuit node to a respective said bit line, and said selection switching element having a control connection connected to the respective said reference word line;
- first switching elements connecting said circuit nodes to said read amplifier;
- a first potential line for supplying a first potential to be stored in said reference cells;
- second switching elements connecting said circuit nodes to said first potential line;
- a second pair of bit lines connected to said second differential read amplifier and, in correspondence with said first pair of bit lines, having memory cells, reference cells, and first and second switching elements;
- two third switching elements each connecting a respective one of said bit lines of said first pair of bit lines to a bit line of said second pair of bit lines;
- and
- a second potential line connected to said circuit nodes of said bit lines of said second bit line pair via corresponding said second switching elements, said second potential line supplying a second potential to be stored in said reference cells of said second pair of bit lines.
9 more elements
A method of operating an integrated memory, which comprises the following steps:
- reading out information from two memory cells and transferring the information via two first bit lines to first inputs of two differential read amplifiers;
- reading out reference information from reference cells and transferring the reference information via second bit lines to second inputs of the read amplifiers;
- amplifying voltages present at the inputs of the read amplifiers with the read amplifiers;
- disconnecting the reference cells from the read amplifiers;
- connecting the reference cells to potential lines;
- and
- transferring potentials from the potential lines via the second bit lines to the reference cells.
4 more elements
Dependencies are inferred from the claim text.