Integrated circuit having an EEPROM and flash EPROM
AssigneeAzalea Microelectronics Corporation
InventorsEungjoon Park, Ali Pourkeramati
Life of this patent
Estimating the term…
Abstract
In accordance with the present invention, a non-volatile integrated circuit memory includes an EEPROM array comprising a plurality of memory cells and a flash EPROM array comprising a second plurality of memory cells, wherein the EEPROM array is capable of being erased byte-by-byte or word-by-word, and the flash EPROM array is capable of being erased sector-by-sector. Both arrays are formed using the same memory cell which is programmed using hot-electron injection and is erased using Fowler-Nordheim tunneling.
Claims18
A non-volatile integrated circuit memory comprising:
- an EEPROM array comprising a first plurality of memory cells;
- and
- a flash EPROM array comprising a second plurality of memory cells,
- wherein a memory cell in each of the first and second plurality of memory cells includes a double-poly stacked-gate having a gate terminal, a source region having a terminal, and a drain region having a terminal,
- wherein the memory cell is programmed by inducing hot electron injection and erased by inducing electron tunneling both through its drain side,
- wherein a drain terminal of each memory cell in the EEPROM array is coupled to a bitline disposed within the EEPROM array through an associated drain-select transistor, and
- wherein the memory cells along a row in the EEPROM array are divided into a predesignated number of groups, the gate terminals of memory cells in each group being connected together and to first and second signal lines through an associated pair of first and second group-select transistors.
A method of operating a non-volatile integrated circuit memory, the method comprising the act of:
- accessing a memory cell in one or both of an EEPROM array and a flash EPROM array disposed within the integrated circuit memory, wherein the memory cell includes a double-poly stacked-gate having a gate terminal, a source region having a terminal and a drain region having a terminal, the memory cells along a row in the EEPROM array being divided into a predesignated number of groups, the memory cells in each group having their gate terminals connected together, the accessing act further comprising:
- selectively coupling a drain terminal of each memory cell in the EEPROM array to a corresponding one of a plurality of bitlines disposed within the EEPROM array through an associated drain-select transistor;
- and
- selectively coupling the gate terminals of the memory cells in each group along the row to a first and a second signal line through a pair of first and second group-select transistors associated with each group.
Dependencies are inferred from the claim text.