Semiconductor integrated circuit device, method of investigating cause of failure occurring in semiconductor integrated circuit device and method of verifying operation of semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a semiconductor chip;
• a memory cell array provided in the semiconductor chip, the memory cell array including nonvolatile memory cells connected to a selection line;
• a driving circuit provided in the semiconductor chip, the driving circuit which drives said selection line;
• an outputting circuit provided in the semiconductor chip, the outputting circuit which outputs data from the memory cell array to outside of the semiconductor chip;
• a first voltage level setting circuit provided in the semiconductor chip, the first voltage level setting circuit including a first determining circuit, a first internal signal generating circuit, and a first decoding circuit, the first determining circuit which determines a first voltage level, the first internal signal generating circuit which generates first internal signals in accordance with outputs of said first determining circuit, and the first decoding circuit which decodes the first internal signals;
• a second voltage level setting circuit provided in the semiconductor chip, the second voltage level setting circuit including a second determining circuit, a second internal signal generating circuit, and a second decoding circuit, the second determining circuit which determines a second voltage level, the second internal signal generating circuit which generates second internal signals in accordance with outputs of the second determining circuit, and the second decoding circuit which decodes the second internal signals;
• and
• an internal voltage generating circuit provided in the semiconductor chip, the internal voltage generating circuit which generates an internal voltage and supplies the internal voltage to the selection line via the driving circuit, the internal voltage generating circuit which changes a level of the internal voltage in accordance with either an output from the first decoding circuit or an output from the second decoding circuit.