Method for programming NAND-type flash memory device using bulk bias
AssigneeSamsung Electronics Co., Ltd.
InventorsJeong-hyuk Choi, Yun-seung Shin
Life of this patent
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Abstract
A method for programming a NAND-type flash memory device is provided. In the method for programming a NAND-type flash memory device having a plurality of strings two dimensionally arranged on the bulk area of a first conductivity type and a plurality of bitlines arranged in parallel on the plurality of strings, a bulk bias corresponding to a reverse bias is applied to the bulk area of the first conductivity type. At least one bitline is selected among the plurality of bitlines. At least one string is selected from among the plurality of strings connected to the selected bitline in parallel. At least one cell is programmed from among the plurality of cells within the selected strings.
Claims12
A method for programming a NAND-type flash memory device having a plurality of bitlines arranged in parallel on a bulk area of a first conductivity type and a plurality of strings two-dimensionally arranged on the bulk area and connected to respective bitlines in parallel, wherein each string has a string selection transistor portion, a cell transistor portion, and a ground selection transistor portion, which are sequentially and serially connected, the string selection transistor portion being controlled by at least one string selection line, the cell transistor portion being controlled by a plurality of wordlines, the ground selection transistor portion being controlled by at least one ground selection line, and the ground selection transistor portion being connected to a common source line, comprising:
- applying a bulk bias corresponding to a reverse bias to the bulk area of the first conductivity type;
- selecting at least one bitline among the plurality of bitlines;
- selecting at least one string among the plurality of strings connected to at least one selected bitline in parallel;
- and
- selecting at least one cell among the plurality of cells constructing the cell transistor portion of the selected string to thereby program at least one selected cell,
- wherein the selecting at least one bitline comprises applying a ground voltage to at least one bitline among the plurality of bitlines and applying a program inhibition voltage to non-selected bitlines excluding the at least one bitline, for a precharge time and a programming time respectively.
A method for programming a NAND-type flash memory device having a plurality of bitlines arranged in parallel on a bulk area of a first conductivity type and a plurality of strings two-dimensionally arranged on the bulk area and connected to respective bitlines in parallel, wherein each string has a string selection transistor portion, a cell transistor portion, and a ground selection transistor portion, which are sequentially and serially connected, the string selection transistor portion being controlled by at least one string selection line, the cell transistor portion being controlled by a plurality of wordlines, the ground selection transistor portion being controlled by at least one ground selection line, and the ground selection transistor portion being connected to a common source line, comprising:
- applying a bulk bias corresponding to a reverse bias to the bulk area of the first conductivity type;
- selecting at least one bitline among the plurality of bitlines;
- selecting at least one string among the plurality of strings connected to at least one selected bitline in parallel;
- and
- selecting at least one cell among the plurality of cells constructing the cell transistor portion of the selected string to thereby program at least one selected cell,
- wherein selecting at least one cell to thereby program at least one selected cell comprises:
- applying a programming voltage to a selected wordline for controlling at least one cell among the plurality of cells within the cell transistor portion of the selected string;
- and
- applying a pass voltage Vpass to a non-selected wordline excluding the selected wordline.
A method for programming a NAND-type flash memory device having a plurality of bitlines arranged in parallel on a bulk area of a first conductivity type and a plurality of strings two-dimensionally arranged on the bulk area and connected to respective bitlines in parallel, wherein each string has a string selection transistor portion, a cell transistor portion, and a ground selection transistor portion, which are sequentially and serially connected, the string selection transistor portion being controlled by at least one string selection line, the cell transistor portion being controlled by a plurality of wordlines, the ground selection transistor portion being controlled by at least one ground selection line, and the ground selection transistor portion being connected to a common source line, comprising:
- applying a bulk bias corresponding to a reverse bias to the bulk area of the first conductivity type;
- selecting at least one bitline among the plurality of bitlines;
- selecting at least one string among the plurality of strings connected to at least one selected bitline in parallel;
- and
- selecting at least one cell among the plurality of cells constructing the cell transistor portion of the selected string to thereby program at least one selected cell, wherein the bulk bias is −1 volts to −2 volts.
Dependencies are inferred from the claim text.