Programming a phase-change memory with slow quench time
AssigneeOvonyx, Inc.
InventorsEungjoon Park, Tyler A. Lowrey
Life of this patent
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Abstract
A memory array is operated by increasing a number of currents through a number of corresponding cells of the array, where each cell has a structural phase-change material to store data for that cell. Each of the currents are increased to an upper level that is sufficiently high that can cause the corresponding cell to be in a first state. Some of the currents are decreased to lower levels at sufficiently high rates that cause their corresponding cells to be programmed to the first state, while others are decreased at sufficiently low rates that cause their corresponding cells to be programmed to a second state.
Claims17
A method for operating a memory array, comprising:
- increasing a plurality of currents through a plurality of corresponding cells of the memory array, each cell having a structural phase-change material to store data for that cell, each of the plurality of currents being increased to an upper level that is sufficiently high that can cause the material in the corresponding cell to be in a first phase;
- and then
- decreasing some of the currents to lower levels, those currents being decreased at sufficiently high rates that cause the materials in their corresponding cells to be programmed to the first phase;
- and
- decreasing some others of the currents to lower levels, those others being decreased at sufficiently low rates that cause the materials in their corresponding cells to be programmed to a second phase.
An integrated circuit device comprising:
- a memory array having a plurality of cells, each cell having a structural phase-change material to store data for that cell;
- and
- waveshaping and timing logic circuitry coupled to the memory array to (1) increase a plurality of currents through a plurality of corresponding cells of the array, each of the plurality of currents to be increased to an upper level that is sufficiently high that can cause the material in the corresponding cell to be in a first phase, and then (2) decrease some of the currents to lower levels, those currents to be decreased at sufficiently high rates that cause the materials in their corresponding cells to be programmed to the first phase, and (3) decrease some others of the currents to lower levels, those others to be decreased at sufficiently low rates that cause the materials in their corresponding cells to be programmed to a second phase.
An integrated circuit device comprising:
- means for storing data according to a first state and a second state;
- means for increasing a current through the storage means to an upper level that is sufficiently high that can cause the storage means to be in the first state, wherein the storage means programs to the first state if the current is decreased from the upper level to a lower level at a sufficiently high rate;
- and
- means for decreasing the current from the upper level to the lower level at a sufficiently low rate that can cause the storage means to be programmed to the second state.
Dependencies are inferred from the claim text.