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US 6,487,107 B1Granted
Retention time of memory cells by reducing leakage current
AssigneeInfineon Technologies AG
InventorRaj Kumar Jain
Life of this patent
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Abstract
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.
Claims19
A memory cell comprising:
- first and second access transistors, each with a gate and first and second terminals
- first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to a first terminal of the second transistor;
- first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
- a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors;
- and
- sense amplifiers coupled to the first and second bit lines, the sense amplifier, during a write logic 0 operation, causes a degraded logic 0 to be stored in the storage transistor.
3 more elements
Dependencies are inferred from the claim text.