Test circuit for semiconductor integrated circuit which detects an abnormal contact resistance
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToshinori Morihara, Hiroki Shimano
Life of this patent
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Abstract
There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.
Claims8
A semiconductor integrated circuit comprising:
- a semiconductor substrate;
- a memory cell including a field effect transistor formed in said semiconductor substrate, and a capacitor having a storage node connected to the source and a cell plate formed on said storage node via a dielectric film;
- a first wiring including said cell plate;
- a first power supply for feeding a first potential so as to maintain a predetermined potential in said cell plate of said capacitor;
- a second wiring having a first node and a second node connected to said first power supply;
- a first contact connected to said first wiring;
- a second contact connected to said first and second nodes;
- a logic circuit which may input a control signal externally at its first input and which connects said first node to its second input;
- a first switching circuit for selecting said first power supply or a second power supply for feeding a second potential, which is higher than a first potential of said first power supply, in response to an output after calculation in said logic circuit, to feed either of said first and second potentials to said first node;
- a second switching circuit for selecting said first power supply or a third power supply for feeding a third potential, which is lower than the first potential of said first power supply, in response to the output after calculation in said logic circuit to feed either of said first and third potentials to said second node;
- and
- a third switching circuit for selecting a fourth power supply for feeding a fourth potential lower than said third potential, or a fifth power supply for feeding a fifth potential, which is higher than said fourth potential and lower than said second potential, in response to the output after calculation in said logic circuit to feed either of said fourth and fifth potentials to said semiconductor substrate associated with said memory cell.
A semiconductor integrated circuit having a multi level interconnect structure comprising:
- a first wiring connected to a transistor region formed in a semiconductor substrate;
- an interlayer dielectric formed on top of this topography;
- first and second contacts formed in said interlayer dielectric;
- a second wiring formed on top of said interlayer dielectric and connected electrically to said first wiring via said first and second contacts;
- and
- switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternatively to said first and second contacts.
Dependencies are inferred from the claim text.