Use of search lines as global bitlines in a cam design

An integrated circuit including a dynamic random access memory content addressable memory (DCAM) array comprising a plurality of memory cells, wherein each of said memory cells comprises:

• storage elements;
• transistors connected to said storage elements;
• match logic connected to said storage elements;
• wordlines connected to, and controlling said transistors;
• bitlines connected to said storage elements through said transistors;
• and
• combined search and global bitlines connected to said match logic and to outputs of at least one local sense amplifier, said memory cells being arranged in columns, said columns comprising:
• multiplexers connected to said combined search and global bitlines;
• data-in lines connected to said multiplexers;
• and
• search-data lines connected to said multiplexers,
• wherein said multiplexers select between said data-in lines and said search-data lines to allow said combined search and global bitlines to be alternatively used as data lines and search lines.

A method of operating a memory cell, comprising:

• multiplexing a search datum and a write datum onto a global bitline coupled to said memory cell;
• determining if there is a match between said search datum appearing on said global bitline and a stored datum stored in said memory cell;
• and
• writing said write datum to said memory cell from said global bitline.

A method of operating a memory array having memory cells, said method comprising:

• multiplexing a search datum and a write datum onto a global bitline coupled to said memory cell;
• determining if there is a match between said search datum appearing on said global bitline and a stored datum stored in said memory cell;
• writing said write datum to said memory cell from said global bitline;
• and
• controlling access between said global bitline and said memory cell using a wordline.