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AssigneesSanyo Electric Co., Ltd., Tottori Sanyo Electric Co., Ltd.
InventorYasuaki Sumi
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A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.
A PLL circuit comprising a producing means (62) for producing reference signals (FR1 to FR5), a variable frequency divider (71, 72) for dividing a frequency of an output signal of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers, and B≦C) to output feedback signals (FP1 to FP5), a phase comparator (65, 67) for comparing phases of the reference signals with phases of the feedback signals, phase comparisons being performed accurately one time out of C.
A PLL circuit comprising a producing means (62) for producing a plurality of reference signals (FR1 to FR5) having different phases, a variable frequency divider (71, 72) for dividing a frequency of an output signal of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers, and B≦C) to output a plurality of feedback signals (FP1 to FP5), phase comparators (65, 67) for comparing phases of the reference signals with phases of the feedback signals to output a plurality of phase comparison signals (U1 to U5, D1 to D5), phase comparisons being performed accurately one time out of C.
Dependencies are inferred from the claim text.