Programmable differential delay circuit with fine delay adjustment

A delay element, comprising:

• a plurality of input and output nodes, including a first and second input node and a first and second output note;
• a first NMOS transistor, wherein a source region is coupled for ground;
• a second PMOS transistor, wherein a source region of a second transistor is coupled to drain region of a first transistor;
• a third PMOS transistor, wherein a gate region is coupled to a second input node, wherein a drain region is coupled to ground;
• a fourth NMOS transistor, wherein a drain region of a fourth transistor is coupled to a source region of a fourth transistor is coupled to the drain of a third transistor, wherein a gate of a fourth transistor is further coupled to a gate of a third, a first and a second transistors;
• a fifth NMOS transistor, wherein a drain region of a fifth transistor is coupled to a first output node, wherein a source region of a fifth transistor is coupled to ground and wherein a gate region is coupled to a second output node and the source region of a fourth transistor;
• a sixth PMOS transistor, wherein a source region is coupled to a source region of a second transistor, wherein drain region is coupled to a drain region of second transistor and a first output node;
• a seventh NMOS transistor, wherein a drain region is coupled to a second output node, wherein a gate region is coupled to a drain region is coupled to a drain region of a fifth transistor and wherein a source region is coupled to ground;
• an eighth PMOS transistor, wherein a source region is coupled to a source region of a sixth transistor, wherein the drain region is coupled to a gate region of a sixth transistor and a second output node, and wherein a gate region is coupled to a drain region of a sixth transistor;
• a ninth PMOS transistor, wherein a source region is coupled to a gate region of a seventh transistor, a drain region is coupled to ground and wherein a gate region is further coupled to a first input node;
• a tenth PMOS transistor, wherein a source region is coupled to a source region of a eighth transistor, wherein a drain region is coupled to the drain region of a eighth transistor and wherein gate region is coupled to a first signal input node;
• an eleventh NMOS transistor, wherein a drain region is coupled to a bias voltage, a source region is coupled to a source region of a ninth transistor and wherein a gate region is further coupled to a first input node;
• and
• a twelfth NMOS transistor, wherein a source region is coupled to ground, a drain region is coupled to a drain region of a tenth transistor and wherein a gate region is coupled to a first input node.