Semiconductor device including a control signal generation circuit allowing reduction in size

A semiconductor device comprising:

• a control signal generation circuit generating a plurality of internal control signals according to a control signal as a reference for performing a series of predetermined operations in said semiconductor device;
• said control signal generation circuit including,
• a delay circuit for delaying said control signal as a reference by a predetermined time period;
• said delay circuit including;
• a plurality of delay units connected in series, and
• a plurality of taps for taking out output signals from said plurality of delay units, respectively, and
• a plurality of signal generation circuits for supplying said plurality of internal control signals as outputs, respectively;
• each of said plurality of signal generation circuits setting a signal level of a corresponding one of said plurality of control signals according to signal levels of at least two of said plurality of delay signals supplied from said plurality of taps, respectively;
• further comprising:
• a plurality of first and second lines each arranged in a different wiring layer;
• wherein
• said plurality of first and second lines are arranged such that they cross each other,
• said plurality of first lines are electrically coupled to said plurality of taps, respectively, and
• said plurality of second lines are electrically coupled to input nodes of said plurality of signal generation circuits, respectively.