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US 6,486,721 B2Granted
Latch control circuit for crossing clock domains
AssigneeSun Microsystems, Inc.
InventorsMark R. Greenstreet, Josephus C. Ebergen
Life of this patent
Estimating the term…
Abstract
A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.
Claims16
A latch control circuit for conveying data from a clock domain of a transmitter to a clock domain of a receiver, comprising:
- a data path circuit having a transmitter latch controlled by a transmitter clock in a first clock domain, a receiver latch controlled by a receiver clock in a second clock domain, and an intermediate latch coupled between the transmitter and receiver latches;
- and
- an interface and control circuit coupled between the transmitter clock and the receiver clock, the interface and control circuit including a clock generator having first and second inputs controlled by delayed versions of the transmitter and receiver clocks and an output coupled to the intermediate latch for controlling the conveyance of a data item from the transmitter latch to the receiver latch.
Dependencies are inferred from the claim text.