Flip-flop circuits having digital-to-time conversion latches therein

An integrated circuit latch, comprising:

• a pair of logic gates that each have first and second data inputs and an output, with the first inputs electrically connected together and responsive to a latching signal and with each of the second inputs electrically connected to an output of the other logic gate in said pair, said pair of logic gates comprising:
• a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a pull-down delay characteristic of the first logic gate by reducing an effective on-state impedance of a first pull-down path therein when an output of said first logic gate is being pulled from a logic 1 value to a logic 0 value by the first pull-down path;
• wherein the first logic gate comprises a first pair of MOS transistors connected source-to-drain in a first totem-pole arrangement;
• wherein the first circuitry comprises a second pair of MOS transistors connected source-to-drain in a second totem-pole arrangement;
• and
• wherein the second totem-pole arrangement is connected in parallel with one of the MOS transistors in the first totem-pole arrangement.

An integrated circuit latch, comprising:

• a pair of logic gates that each have first and second data inputs and an output, with the first inputs electrically connected together and responsive to a latching signal and with each of the second inputs electrically connected to an output of the other logic gate in said pair, said pair of logic gates comprising:
• a first logic gate having first circuitry therein that, in response to a first control signal, adjusts a pull-down delay characteristic of the first logic gate by reducing an effective on-state impedance of a first pull-down path therein when an output of said first logic gate is being pulled from a logic 1 value to a logic 0 value by the first pull-down path;
• and
• a second logic gate having second circuitry therein that, in response to a second control signal, adjusts a pull-down delay characteristic of the second logic gate by reducing an effective on-state impedance of a second pull-down path therein when an output of said second logic gate is being pulled from a logic 1 value to a logic 0 value by the second pull-down path;
• wherein the first and second control signals are complementary data signals;
• and
• wherein the latching signal is a clock signal;
• wherein the first logic gate comprises a first pair of MOS transistors connected source-to-drain in a first totem-pole arrangement;
• wherein the first circuitry comprises a second pair of MOS transistors connected source-to-drain in a second totem-pole arrangement;
• and
• wherein the second totem-pole arrangement is connected in parallel with one of the MOS transistors in the first totem-pole arrangement.

A multi-stage latch circuit, comprising:

• a first logic gate having a first data input and an output and comprising first circuitry that adjusts a pull-down delay characteristic and/or pull-up delay characteristic of said first logic gate in response to a first control signal;
• a second logic gate having a first data input and an output electrically coupled to the output and the first data input of said first logic gate, respectively;
• a third logic gate having a first data input electrically coupled to the output of said first logic gate, a second data input and an output;
• and
• a fourth logic gate having a first data input electrically coupled to the output of said second logic gate, a second data input electrically coupled to the output of said third logic gate and an output electrically coupled to the second data input of said third logic gate.

A flip-flop circuit that latches data in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein either the delay time of said first delay stage or the delay time of said second delay stage is controlled by the data and varies;
• and
• wherein the flip-flop circuit further comprises a second latch circuit for latching a signal output from the output of the first logic gate and a signal output from the output of the second logic gate.

A flip-flop circuit that latches data in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein either the delay time of said first delay stage or the delay time of said second delay stage is controlled by the data and varies;
• and
• wherein each of the first and second delay stages includes a one bit digital-to-time converter (DTC).

A digital magnitude comparator that compares a magnitude of a first digital signal with a magnitude of a second digital signal in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein a delay time of the first delay stage is controlled by the first digital signal and varies and a delay time of the second delay stage is controlled by the second digital signal and varies;
• and
• wherein the digital magnitude comparator further comprises a second latch circuit for latching a signal output from the output of the first logic gate and a signal output from the output of the second logic gate.

A digital magnitude comparator that compares a magnitude of a first digital signal with a magnitude of a second digital signal in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein a delay time of the first delay stage is controlled by the first digital signal and varies and a delay time of the second delay stage is controlled by the second digital signal and varies;
• and
• wherein each of the first and second delay stages comprises a N (N is a natural number) bit DTC.

An analog voltage comparator that compares a magnitude of a first analog voltage with a magnitude of a second analog voltage in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein a delay time of the first delay stage is controlled by the first analog voltage and varies and a delay time of the second delay stage is controlled by the second analog voltage and varies;
• and
• wherein the analog voltage comparator further comprises a second latch circuit for latching a signal output from the output terminal of the first logic gate and a signal output from the output terminal of the second logic gate.

An analog voltage comparator for comparing the magnitude of a first analog voltage with the magnitude of a second analog voltage in response to a clock signal, comprising:

• first and second delay stages having respective input terminals that receive the clock signal;
• and
• a first latch circuit comprising a first logic gate having a first input terminal that receives a signal output by the said first delay stage and a second logic gate having a first input terminal that receives a signal output by said second delay stage;
• wherein an output of the first logic gate is connected to a second input of the second logic gate and an output of the second logic gate is connected to a second input of the first logic gate;
• wherein a delay time of the first delay stage is controlled by the first analog voltage and varies and a delay time of the second delay stage is controlled by the second analog voltage and varies;
• and
• wherein each of the first and second delay stages comprises a voltage-to-time converter (VTC).