Divider with cycle time correction
AssigneeFujitsu Limited
InventorsToshiaki Kinoshita, Kunio Aduma
Life of this patent
Estimating the term…
Abstract
The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the counter 41 as a reference value RV in response to activation of a capture signal CAP; a comparator 43 activating a coincidence signal EQ when CN=RV, a control register 44 including a bit outputting a clear signal CLR2, a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits 45 and 46 activating the clear signal CLR1 when the clear signal CLR2 is active or when the enable signal EN and the coincidence signal EQ are both active.
Claims6
A divider with cycle time correction comprising:
- a counter counting a clock and initialized by activation of a first initialization signal;
- a reference register connected to said counter to store a count of said counter in response to activation of a capture signal;
- a comparator activating a coincidence signal when said count and an output value of said reference register are equal to each other;
- and
- a control circuit activating said first initialization signal in response to activation of a second initialization signal or activation of both an enable signal and said coincidence signal, said control circuit activating said capture signal after a predetermined time has elapsed from activation of said second initialization signal.
An oscillator with cycle time correction, comprising:
- an oscillator generating a clock;
- a counter counting said clock and initialized by activation of a first initialization signal;
- a reference register connected to said counter to store a count of said counter in response to activation of a capture signal;
- a comparator activating a coincidence signal when said count and an output value of said reference register is equal to each other;
- and
- a control circuit activating said first initialization signal in response to activation of a second initialization signal or activation of both an enable signal and said coincidence signal, said control circuit activating said capture signal after a predetermined time has elapsed from activation of said second initialization signal.
Dependencies are inferred from the claim text.