System and method for achieving fast switching of analog voltages on large capacitive load

In a driver for driving a capacitive load, the driver having a load buffer with an input and an output coupled to the capacitive load, and a reserve circuit with a reserve capacitor and a first switch capable of coupling the reserve capacitor to the capacitive load, a method of operating the driver comprising steps of:

• changing an input voltage (VIN) applied to the input of the load buffer;
• operating the load buffer to drive an output voltage (VOUT) applied to the capacitive load between a first voltage level (V1) and a second voltage level (V2) in response to the change in VIN;
• and
• closing the first switch to couple the reserve capacitor to the capacitive load,
• whereby time for the capacitive load to transition between V1 and V2 is reduced.

A non-volatile memory system for storing information therein, the non-volatile memory system comprising;

• a plurality of storage elements having a plurality of Field Effect Transistors (FETs) with gates electrically isolated from sources and drains of the FETs;
• and
• a driver coupled to the gates to sequentially drive the gates of the plurality of FETs between a voltage for determining the state of said storage elements (V1) and a programming voltage (V2), the driver comprising:
• a load buffer having an input adapted to receive an input voltage (VIN), and an output adapted to couple an output voltage (VOUT) to the gates, the load buffer configured to drive VOUT between V1 and V2 in response to a change in VIN;
• and
• means adapted to couple to the gates for reducing time for VOUT to transition between V1 and V2.

A method of driving a capacitive load from a first voltage level (V1) to a second voltage level (V2), the method comprising steps of:

• providing a reserve capacitor;
• charging the reserve capacitor a predetermined voltage;
• and
• coupling the reserve capacitor to the capacitive load to drive the capacitive load from V1 to V2,
• whereby time for the capacitive load to transition between V1 and V2 is reduced.

A driver for driving a capacitive load, the driver comprising:

• a load buffer having an input adapted to receive an input voltage (VIN), and an output adapted to couple an output voltage (VOUT) to the capacitive load, the load buffer configured to drive VOUT between a first voltage level (V1) and a second, higher voltage level (V2) in response to a change in VIN;
• and
• a reserve circuit configured to reduce time for VOUT to transition between V1 and V2, the reserve circuit comprising:
• a first reserve capacitor (CRES—A);
• a first reserve buffer having an input adapted to receive a first input voltage (VRES—IN—A), and an output adapted to couple a first output voltage (VRES—OUT—A) to CRES—A to charge CRES—A;
• a second reserve capacitor (CRES—B);
• a second reserve buffer having an input adapted to receive a second input voltage (VRES—IN—B), and an output adapted to couple a second output voltage (VRES—OUT—B) to CRES—B to charge CRES—B;
• a switch whereby the CRES—A and CRES—B can be alternately coupled to the capacitive load;
• and
• a controller whereby the switch can be operated, the controller configured to operate the switch to alternately couple CRES—A and CRES—B to the capacitive load when VOUT is being driven between V1 and V2.