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US 6,486,713 B2Granted
Differential input buffer with auxiliary bias pulser circuit
AssigneeMicron Technology, Inc.
InventorsJeffrey P. Wright, Alan J. Wilson
Life of this patent
Estimating the term…
Abstract
An integrated circuit clock buffer is described which includes a pulser circuit having a delayed feedback to provide a pulsed signal in response to a transition in the external clock signal. The pulser circuit includes a delay element having an output node coupled to the input node of an inverter. The delay element and inverter are coupled between a first and second transistor. The buffer circuit generates non-skewed internal clock signals.
Claims26
A buffer circuit comprising:
- a first input node for receiving a digital signal;
- a controllable buffer circuit coupled to the first input node responsive to an enable signal, the controllable buffer circuit providing an output signal in response to the digital signal when the enable signal is in a first state, and the controllable buffer circuit being disabled when the enable signal is in a second state, said buffer circuit having a bias node;
- and
- a pulser circuit coupled to said bias node for providing a pulse signal to said bias node in response to said enable signal switching to said first state, wherein said pulser circuit comprises a first and second transistor connected in series between said bias node and a source of potential, said first transistor directly receiving said enable signal at a gate thereof, said second transistor receiving said enable signal at a gate thereof after it passes through at least a delay element.
1 more element
A memory device comprising:
- a memory array containing a plurality of memory cells;
- and
- a buffer circuit comprising:
- a first input node for receiving a digital signal;
- a controllable buffer circuit coupled to the first input node responsive to an enable signal, the controllable buffer circuit providing an output signal in response to the digital signal when the enable signal is in a first state, and the controllable buffer circuit being disabled when the enable signal is in a second state said buffer circuit having a bias node;
- and
- a pulser circuit coupled to said bias node for providing a pulse signal to said bias node in response to said enable signal switching to said first state, wherein said pulser circuit comprises a first and second transistor connected in series between said bias node and a source of potential, said first transistor directly receiving said enable signal at a gate thereof, said second transistor receiving said enable signal at a gate thereof after it passes through at least a delay element.
4 more elements
A processor based system comprising:
- a central processing unit;
- a memory device coupled to said central processing unit to receive data from and supply data to said central processing unit, said memory device comprising:
- a buffer circuit comprising:
- a first input node for receiving a digital signal;
- a controllable buffer circuit coupled to the first input node responsive to an enable signal, the controllable buffer circuit providing an output signal in response to the digital signal when the enable signal is in a first state, and the controllable buffer circuit being disabled when the enable signal is in a second state said buffer circuit having a bias node;
- and
- a pulser circuit coupled to said bias node for providing a pulse signal to said bias node in response to said enable signal switching to said first state, wherein said pulser circuit comprises a first and second transistor connected in series between said bias node and a source of potential, said first transistor directly receiving said enable signal at a gate thereof, said second transistor receiving said enable signal at a gate thereof after it passes through at least a delay element.
4 more elements
A method of reducing clock skew comprising the acts of:
- providing a first input node for receiving a digital signal;
- providing a controllable buffer circuit coupled to the first input node responsive to an enable signal, the controllable buffer circuit providing an output signal in response to the digital signal when the enable signal is in a first state, and the controllable buffer circuit being disabled when the enable signal is in a second state, said buffer circuit having a bias node;
- and
- providing a pulser circuit coupled to said bias node for providing a pulse signal to said bias node in response to said enable signal switching to said first state, wherein said pulser circuit comprises a first and second transistor connected in series between said bias node and a source of potential, said first transistor directly receiving said enable signal at a gate thereof, said second transistor receiving said enable signal at a gate thereof after it passes through at least a delay element.
1 more element
Dependencies are inferred from the claim text.