Differential voltage magnitude comparator

A circuit comprising:

• a first transistor and a second transistor coupled in series between a first supply node and a first output node;
• a third transistor and a fourth transistor coupled in series between the first supply node and the first output node;
• a fifth transistor and a sixth transistor coupled in series between the first supply node and a second output node;
• a seventh transistor and an eighth transistor coupled in series between the first supply node and the second output node;
• a ninth transistor and a tenth transistor coupled in series between a second supply node and the first output node;
• a eleventh transistor and a twelfth transistor coupled in series between the second supply node and the first output node;
• a thirteenth transistor and a fourteenth transistor coupled in series between the second supply node and the second output node;
• a fifteenth transistor and a sixteenth transistor coupled in series between the second supply node and the second output node;
• said first through eighth transistors coupled to receive a differential input signal and said ninth through sixteenth transistors coupled to receive a differential reference signal, said sixteen transistors coupled to provide a differential output at the first and second output nodes in which the output is in a first differential state if a differential magnitude between pair of inputs of the differential input signal is below a reference magnitude established by the differential reference signal, but the output is in a second differential state if the differential magnitude between the pair of inputs of the differential input signal is above the reference magnitude.

An apparatus comprising:

• a receiver to be coupled to a differential serial bus to receive data present on the bus;
• a squelch detector coupled to said receiver and also to be coupled to the differential serial bus, said detector including:
• (a) a first comparator coupled to receive the differential serial data as its differential input signal, said first comparator to have parallel branches of active components in which pair of input lines for the differential input signal are separately coupled to first and second branches respectively, but both pair of input lines are coupled to third and fourth branches;
• (b) a second comparator coupled to receive a differential reference signal, said second comparator to have parallel branches of active components in which pair of reference lines for the differential reference signal are separately coupled to fifth and sixth branches respectively, but both pair of reference lines are coupled to seventh and eighth branches,
• said first and second comparators coupled to provide an output in which the output is in a first state if a differential magnitude between the two input lines of the differential input signal is below a reference magnitude established by the differential reference signal, but the output is in a second state if the differential magnitude between the two input lines of the differential input signal is above the reference magnitude, said two comparators arranged to provide the comparison and output in a single stage;
• and
• said squelch detector activating the receiver to receive data when data is present on the bus.

A method comprising:

• receiving a differential input signal to a four branch comparator in which one input of the differential input signal is coupled to first, third and fourth branches and other input of the differential input signal is coupled to second, third and fourth branches;
• receiving a differential reference signal to another four branch comparator in which the differential reference signal is coupled to fifth, seventh and eighth branches and other input of the differential reference signal is coupled to sixth, seventh and eighth branches;
• comparing a magnitude difference of the differential input signal to the magnitude difference of the differential reference signal;
• generating an output in which the output is in a first state if the magnitude difference of the differential input signal is below the magnitude difference of the differential reference signal, but the output is in a second state if the magnitude difference between the differential input signal is above the magnitude difference of the differential reference signal, the magnitude comparison and output are generated in a single symmetrical stage.

A system comprising:

• a receiver to be coupled to a differential serial bus to receive data present on the bus, said receiver including a squelch detector to be coupled to the differential serial bus, said detector including:
• (a) a first comparator coupled to receive the differential serial data as its differential input signal, said first comparator to have parallel branches of active components in which pair of input lines for the differential input signal are separately coupled to first and second branches respectively, but both pair of input lines are coupled to third and fourth branches;
• (b) a second comparator coupled to receive a differential reference signal, said second comparator to have parallel branches of active components in which pair of reference lines for the differential reference signal are separately coupled to fifth and sixth branches respectively, but both pair of reference lines are coupled to seventh and eighth branches;
• said first and second comparators coupled to generate an output in which the output is in a first state if a differential magnitude between the two input lines of the differential input signal is below a reference magnitude established by the differential reference signal, but the output is in a second state if the differential magnitude between the two input lines of the differential input signal is above the reference magnitude, said two comparators arranged to provide the comparison and output in a single stage;
• said squelch detector activating said receiver to receive data when data is present on the bus;
• and
• a processor coupled to said receiver to process the received data.