Logic circuit and its forming method

#1. Field of the Invention

#The present invention relates to a fast logic circuit formed using selector circuits, as well as a method for forming such the logic circuit.

#2. Description of Related Art

#FIG. 1 shows an embodiment of the present invention.

#FIG. 2 shows another embodiment of the present invention.

#FIG. 3 is a circuit diagram of a selector.

#Hereunder, the logic circuits of the present invention will be described in detail with reference to some embodiments shown in the accompanying drawings. The same reference numbers will be used in those accompanying drawings to indicate the same items or similar items.

#<First Embodiment>

#At first, an embodiment of the present invention will be described in accordance with the a-row shown in FIG. 1. Each of the selectors (S5 and S6 of C0 and S1 to S3 of C1, etc.) shown in the a-row in FIG. 1 has a logic function shown with a Boolean expression (E100 in the a-row) in FIG. 3. In other words, if the value of the control input S is “1”, the input II is selected and an object input signal is output to the output O. If the value of the control input S is “0”, the input I0 is selected and the object input signal is output to the output O. In each of the circuits C100 to C102 shown in FIG. 3, for example, this 2-input 1-output selector is composed of various types of circuits. Of those circuits C100 to C102, the circuit C100 has a selector part (transistors T100 and T101) composed only of n-channel field-effect transistors. The circuit C100 is shown in the reference document 1. In this circuit C100, transistors T102, T103, and T106 are inserted as buffers so as to be used mainly for reducing the delay time of the circuit. These transistors are omissible if another selector circuit is provided in the following stage.