Embedded memory blocks for programmable logic

A programmable logic integrated circuit comprising:

• a top row of memory blocks formed along a top edge of the integrated circuit;
• a bottom row of memory blocks formed along a bottom edge of the integrated circuit;
• a plurality of logic blocks, arranged in rows and columns, programmably configurable to implement logic functions, formed between the top and bottom rows of memory blocks;
• a plurality of horizontal programmable interconnect lines, programmably coupled to the logic blocks;
• and
• a plurality of vertical programmable interconnect lines, programmably coupled to the logic blocks.

A programmable logic integrated circuit comprising:

• a plurality of programmable interconnect lines arranged in rows and columns;
• a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions;
• a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block;
• and
• a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein the output control signals are coupled to the embedded array via the programmable interconnect lines.

A programmable logic integrated circuit comprising:

• a plurality of programmable interconnect lines arranged in rows and columns;
• a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions;
• a first row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the first row of embedded array blocks are formed along a first edge of the integrated circuit and each embedded array block includes a RAM block;
• and
• a second row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the second row of embedded array blocks are formed along a second edge of the integrated circuit, opposite, of the first edge, and each embedded array block includes a RAM block, wherein the logic array blocks are formed between the first and second rows of embedded array blocks.

A programmable logic integrated circuit comprising:

• a plurality of programmable interconnect lines arranged in rows and columns;
• a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions;
• a first row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the first row of embedded array blocks are formed along a first edge of the integrated circuit and each embedded array block includes a RAM block;
• a second row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the second row of embedded array blocks are formed along a second edge of the integrated circuit, opposite of the first edge, and each embedded array block includes a RAM block;
• and
• a plurality of IO bands comprising input and output circuitry, formed between the first and second rows of memory blocks.