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US 6,486,701 B1Granted
CPLD high speed path
AssigneeCypress Semiconductor Corporation
InventorRoger Bettman
Life of this patent
Estimating the term…
Abstract
An apparatus comprises two or more memory elements connected in parallel and programmed alike, where the memory elements comprise a high speed path of a programmable logic device.
Claims20
An apparatus comprising:
- two or more memory elements having inputs and outputs connected in parallel and programmed alike, wherein said two or more memory elements comprise a high speed path of a programmable logic device.
An apparatus comprising:
- means for programming two or more memory elements alike;
- and
- means for connecting inputs and outputs of said two or more memory elements in parallel, wherein said memory elements comprise a high speed path of a programmable logic device.
A method for constructing a high speed path in a programmable logic device comprising the steps of:
- (A) connecting inputs and outputs of two or more memory elements in parallel;
- and
- (B) programming said memory elements alike.
Dependencies are inferred from the claim text.