Integrated circuit devices having a delay locked loop that is configurable for high-frequency operation during test and methods of operating same

An integrated circuit device, comprising:

• a first selection circuit that receives an internal clock signal at a first input terminal thereof and a feedback signal at a second input terminal thereof, and provides one of the internal clock signal and the feedback signal at an output terminal thereof in response to a test mode signal;
• a second selection circuit that receives a first external clock signal at a first input terminal thereof and a reference clock signal at a second input terminal thereof, and provides one of the first external clock signal and the reference clock signal at an output terminal thereof in response to the test mode signal;
• a phase detector circuit having first and second input terminals that are electrically connected to the output terminals of the first and second selection circuits, respectively, and generates a phase comparison signal at an output terminal thereof, the phase comparison signal being indicative of a phase difference between signals on the first and second input terminals of the phase detector circuit;
• and
• a synchronization circuit that adjusts a phase of the internal clock signal based on the phase comparison signal.

An integrated circuit device, comprising:

• means for selecting one of an internal clock signal and a feedback signal as a first input signal in response to a test mode signal;
• means for selecting one of a first external clock signal and a reference clock signal as a second input signal in response to the test mode signal;
• means for generating a phase comparison signal that is indicative of a phase difference between the first and second input signals;
• and
• means for adjusting a phase of the internal clock signal based on the phase comparison signal.

A method of operating an integrated circuit device, comprising the steps of:

• providing a test mode signal;
• generating a control signal in response to the test mode signal;
• operating an oscillator circuit in response to the test mode signal to generate a clock signal;
• and
• operating a delay locked loop (DLL) circuit in one of a test mode and a normal mode in response to the control signal and the clock signal.

A method of operating an integrated circuit device, comprising the steps of:

• selecting one of an internal clock signal and a feedback signal as a first input signal in response to a test mode signal;
• selecting one of a first external clock signal and a reference clock signal as a second input signal in response to the test mode signal;
• generating a phase comparison signal that is indicative of a phase difference between the first and second input signals;
• and
• adjusting a phase of the internal clock signal based on the phase comparison signal.