US 6,486,560 B1 · Semiconductor device fabricated by a method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution

Abstract

A semiconductor device fabricated by a method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution. The method reduces the drift velocity, thereby decreasing the Cu migration rate in addition to void formation rate. The method comprises: depositing a Cu seed layer in the via; treating the Cu seed layer in a chemical solution, selectively forming a Cu—Ca—X conformal layer on the Cu seed layer, wherein X denotes at least one contaminant; and processing the Cu—Ca—X conformal layer, effecting a thin Cu—Ca conformal layer on the Cu seed layer; annealing the thin Cu—Ca conformal layer onto the Cu seed layer, removing the at least one contaminant, thereby forming a contaminant-reduced Cu—Ca alloy surface on the Cu seed layer; electroplating the contaminant-reduced Cu—Ca alloy surface with Cu, thereby forming a contaminant-reduced Cu—Ca/Cu interconnect structure; annealing the at least one contaminant-reduced Cu—Ca/Cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure; and chemical mechanical polishing the at least one virtually void-less and contaminant-reduced Cu—Ca/Cu interconnect structure in the semiconductor device.

Claims12

Dependent claims

A semiconductor device having a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure for reducing electromigration therein, comprising:

a semiconductor substrate, the substrate having at least one via formed therein;
and
a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure, said interconnect structure comprising:
a Cu seed layer deposited in the at least one via;
a contaminant-reduced calcium-doped copper (Cu—Ca) alloy surface deposited on the Cu seed layer;
and
at least one Cu interconnect line deposited in the at least one via and over the contaminant-reduced Cu—Ca alloy surface,
the Cu seed layer comprising a plating treatment using a chemical solution for forming a Cu—Ca—X conformal layer on the Cu seed layer, X comprising at least one contaminant, and
the Cu—Ca—X conformal layer comprising an annealing treatment for forming the contaminant-reduced Cu—Ca alloy surface on the Cu seed layer and for facilitating forming the virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure.

6 more elements

A semiconductor device having a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure for reducing electromigration therein, comprising:

a semiconductor substrate, the substrate having at least one via formed therein, each at least one via having a barrier layer formed therein;
and
a virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure, said interconnect structure comprising:
a Cu seed layer deposited in the at least one via;
a contaminant-reduced calcium-doped copper (Cu-Ca) alloy surface deposited on the Cu seed layer;
and
at least one Cu interconnect line deposited in the at least one via and over the contaminant-reduced Cu—Ca alloy surface,
the Cu seed layer comprising a plating treatment using a chemical solution for forming a Cu—Ca—X conformal layer on the Cu seed layer, X comprising at least one contaminant,
the Cu—Ca—X conformal layer comprising an annealing treatment for forming the contaminant-reduced Cu—Ca alloy surface on the Cu seed layer and for facilitating forming the virtually voidless contaminant-reduced copper-calcium alloy surface on copper (Cu—Ca/Cu) interconnect structure,
the barrier layer comprising tantalum (Ta),
the Cu seed layer being deposited by a technique selected from a group consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD),
the at least one interconnect line being dual inlaid,
the chemical solution comprising an electroless plating solution,
the electroless plating solution comprising:
a. at least one Cu salt,
b. at least one Ca salt,
C. at least one complexing agent,
d. at least one reducing agent,
e. at least one pH adjuster, and
f. at least one surfactant,
the at least one contaminant being selected from a group consisting essentially of carbon (C), sulphur (S), and oxygen (O),
the annealing treatment comprising a temperature range of 250° C. to 450° C. in an environment selected from a group consisting essentially of a vacuum, an inert gas, and a reducing ambient, and
the contaminant-reduced Cu—Ca alloy surface being Cu-rich and comprises a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.

20 more elements

Dependencies are inferred from the claim text.

Semiconductor device fabricated by a method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution

Life of this patent

Semiconductor device fabricated by a method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution

Life of this patent

Abstract

Claims12