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AssigneeInternational Business Machines Corporation
InventorsCharles R. Davis, Daniel Charles Edelstein, John C. Hay, Jeffrey C. Hedrick, Christopher Jahnes, Vincent McGahay, Henry A. Nye, III
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A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.
A multi-level, coplanar interconnect structure on an integrated circuit chip, comprising:
A multi-level, coplanar interconnect structure on an integrated circuit chip, comprising:
Dependencies are inferred from the claim text.