Molded body for PBGA and chip-scale packages

#1. Field of the Invention

#The present invention relates in general to electronic packages and methods of forming thereof, and in particular pertains to an electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages.

#In essence, a particular type of electronic package which consists of a PBGA (plastic ball grid array) package, and which is applicable to chip-scale or near-chip-scale applications, and is essentially constituted of a chip mounted on an organic, wire carrier or circuitized substrate the size of which may extend beyond the peripheral dimensions of the semiconductor chip. The foregoing relates to both wire-bond and flip chip packages and wherein in order to protect the semiconductor chip from the deleterious or debilitating effects of the environment, it is generally desirable to form an insulating body about the chip, this body generally being in the form of a molded epoxy material forming an encapsulant. Generally, as is well known in the technology, interfacial stresses which are generated between the encapsulating molded material, such as the epoxy which may be a thermoset plastic resin, and the circuitized substrate or chip carrier, can be quite considerable in magnitude and may result in delamination of the components as a result of exposure to moisture or during thermal cycling. This will adversely affect the reliability and possibly even completely destroy the electrical interconnections of the electronic package and the functional integrity thereof, leading to potentially extensive financial and economic losses. Heretofore, when applying the molded material producing the protective structure encompassing the semiconductor chip and forming the physical bond with the carrier or circuitized substrate on which the chip is positioned, the molded material has been confined to engagement with the surface on the side of the carrier or substrate on which the semiconductor chip is mounted, whereby the opposite or distal side of the carrier, on which there is normally disposed an array of solder balls (BGA's) is left unencapsulated so as to provide electrical connecting access for the solder balls. Although the encapsulation of the semiconductor chip and the resulting bonding with the circuitized substrate or carrier is effected by a molded compound generally constituted of an epoxy, the tendency in industry, at this time has been a shifting towards the use of mold compounds or bodies forming the encapsulate for the electronic package which has a lower coefficient of thermal expansion (CTE) than heretofore, whereby the interfacial stresses which extend normal to the surface of the carrier or circuitized substrate facing towards the semiconductor chip are reduced in the region extending about the periphery of the semiconductor chip. This, in essence, increases the bending of the electronic semiconductor chip-mounting package and decreases the fatigue life expectancy of the ball grid arrays (BGA). Although the stresses which are generated as a result of bending are ordinarily not a problem to the degree in chip-scale packages as they would be in larger PBGA's, these stresses must be still minimized due to the effect on BGA fatigue and to enable an increase in their length of service life. The fatigue life of such BGA's represents a particular problem for chip-scale packages, inasmuch as the solder ball size and the pitch between balls must be decreased in order to be able to provide sufficient numbers of interconnections with the small package size, whereby both of these decreases in pitch and size result in a shorter fatigue life for the structure.

#Reference may now be made to the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings; in which:

#FIG. 1 illustrates, generally diagrammatically, a sectional view of a first embodiment of the electronic package of the invention, illustrating the assembled semiconductor chip, circuitized substrate and the thermally conductive encapsulant of the electronic package;

#FIG. 2 illustrates a modified embodiment of an electronic package, represented in a view similar to FIG. 1, showing encapsulant-filled the through holes as formed in the circuitized substrate;

#Referring in specific detail to the drawings, FIG. 1 illustrates in a transverse diagrammatic sectional representation electronic package 10 which includes a semiconductor chip or chip package 12 positioned above a circuitized substrate member 14, the latter of which is dimensioned so as to preferably extend beyond the peripheral dimensions of the semiconductor chip 12.

#The surface 16 of the circuitized substrate member 14 facing towards the surface of the semiconductor chip 12 may have an array of solder balls 18 arranged in the spacing therebetween, and which solder balls are encapsulated in an underfill material 20, as is well known in the electronic packaging technology.

#Arranged at the opposite side of the semiconductor chip 12 at a predetermined spacing therewith is a heat spreader 22, which may be in the form of a cap member constituted of a thermally conductive material so as to provide a heat sink, and wherein the peripheral dimensions of the heat spreader or cap 22 may extend beyond those of the semiconductor chip 12.