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US 6,486,546 B2Granted
Low profile multi-IC chip package connector
AssigneeMicron Technology, Inc.
InventorsWalter L. Moden, Jerrold L. King, Jerry M. Brooks
Life of this patent
Estimating the term…
Abstract
A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.
Claims60
A package comprising:
- a substrate having a plurality of circuits;
- a plurality of encapsulated semiconductor devices, each encapsulatedsemiconductor device having an upper surface, a lower surface, a first lateral edge located between said upper surface and said lower surface, a second lateral edge located between said upper surface and said lower surface, and a plurality of outer leads extending from said first lateral edge and said second lateral edge;
- a cage for partially enclosing and retaining said plurality of encapsulated semiconductor devices in a stack, said cage having a wall located adjacent said plurality of encapsulated semiconductor devices in said stack, said cage including:
- a flexible member generally perpendicular to said upper surface and said lower surface of said encapsulated semiconductor device of said stacked plurality of encapsulated semiconductor devices, said flexible member comprising a layer of material on an inner surface of a portion of said cage, a second flexible member overlying said layer of material attached thereto, and at least one node on an interior of said cage wall adjacent said plurality of encapsulated semiconductor devices retaining said plurality of encapsulated semiconductor devices in said stack in said cage, said at least one node comprising a removable polymeric adhesive attaching said plurality of encapsulated semiconductor devices in said stack to said cage;
- and
- a conductive bus line formed on said flexible member, said conductive bus line extending substantially perpendicular to said plurality of encapsulated semiconductor devices in said stack, contacting an equivalent outer lead of said plurality of outer leads of each encapsulated semiconductor device of said plurality of encapsulated semiconductor devices, and connecting to said at least one circuit of said substrate.
3 more elements
A semiconductor device package, comprising:
- a substrate having circuits thereon;
- a stacked plurality of packaged encapsulated semiconductor devices, each packaged encapsulated semiconductor device having an upper major surface and a lower major surface having lateral edges therebetween and a plurality of outer leads extending from said lateral edges;
- a cage of members for partially enclosing and retaining said stacked plurality of packaged encapsulated semiconductor devices in a stack, said cage including:
- a layer of material on an inner surface of one of said members, a flexible member overlying said layer of material attached thereto, and at least one node on an interior of a connected member adjacent said stacked plurality of packaged encapsulated semiconductor devices in said cage, said at least one node comprising a rib substantially parallel to one of said upper major surface and said lower major surface of one semiconductor device of said plurality of packaged encapsulated semiconductor devices, said rib comprising a removable polymeric adhesive for attaching said semiconductor device to said cage;
- and
- conductive bus line formed on said flexible member, said conductive bus line generally perpendicular to said upper and lower major surfaces of each of said stacked plurality of packaged encapsulated semiconductor devices and contacting said plurality of outer leads of each of said stacked plurality of packaged encapsulated semiconductor devices connected to a circuit of said circuits of said substrate.
3 more elements
A package for high-speed semiconductor devices, comprising:
- a substrate having circuits thereon;
- a stacked plurality of packaged encapsulated semiconductor devices, each packaged encapsulated semiconductor device having opposed major upper and lower surfaces having lateral edges therebetween and a plurality of outer leads extending from said lateral edges;
- a cage of members partially enclosing and retaining said stacked plurality of packaged encapsulated semiconductor devices;
- a flexible member generally perpendicular to said opposed major upper and lower surfaces, said flexible member comprising a layer of material on an inner surface of one of said cage flexible members and another flexible member overlying said layer of material attached thereto;
- a conductive bus line formed on said flexible member, said conductive bus line generally perpendicular to said opposed major upper and lower surfaces of said stacked plurality of packaged encapsulated semiconductor devices, contacting said plurality of outer leads of each of said stacked plurality of packaged encapsulated semiconductor devices, and connected to said circuits said substrate;
- and
- at least one node on an interior wall of said cage adjacent a semiconductor device of said stacked plurality of packaged encapsulated semiconductor devices retaining said semiconductor device in said cage, said at least one node comprising a rib substantially parallel to a major surface of said major upper and lower surfaces of said semiconductor device, said rib comprising a removable polymeric adhesive fixing said plurality of packaged encapsulated semiconductor devices to said cage.
4 more elements
A package for high-speed semiconductor devices, comprising:
- a substrate having circuits thereon;
- a stacked plurality of encapsulated semiconductor device packages, each encapsulated semiconductor device package having opposed major upper and lower surfaces having lateral edges therebetween and a plurality of outer leads extending from said lateral edges;
- a cage of members for partially enclosing and retaining said stacked plurality of encapsulated semiconductor device packages in a stack;
- a flexible member generally perpendicular to said opposed major upper and lower surfaces, said flexible member comprising a layer of material on an inner surface of one of said flexible members and another flexible member overlying said layer of material and attached thereto;
- a conductive bus line formed on said flexible member, said conductive bus line generally perpendicular to said opposed major upper and lower surfaces of said stacked plurality of encapsulated semiconductor device packages, contacting said plurality of outer leads of each of said stacked plurality of encapsulated semiconductor device packages and connected to said circuits of said substrate;
- and
- at least one node on an interior wall of said cage adjacent a semiconductor device package of said plurality of encapsulated semiconductor device packages retaining said semiconductor device package in said cage, said at least one node comprising a rib substantially parallel to a major surface of said major upper and lower surfaces of said semiconductor device package, said rib comprising a removable polymeric adhesive attaching said semiconductor device package to said cage.
4 more elements
Dependencies are inferred from the claim text.