Contact structure with a lower interconnection having t-shaped portion in cross section and method for forming the same

A contact structure formed in a peripheral circuit area or a logic circuit area of a semiconductor device having a cell array area with a plurality of memory cells and the peripheral or logic circuit area, the contact structure comprising:

• a lower interconnection formed of the same material as a capacitor upper electrode of the plurality of memory cells;
• an interlayer dielectric layer formed on the lower interconnection and having a contact hole exposing a region of the lower interconnection;
• and
• an upper interconnection formed on the interlayer dielectric layer, filling the contact hole and being electrically connected to the lower interconnection,
• wherein the lower interconnection has a T-shaped portion in cross section, the T-shaped portion having a larger width than the bottom of the contact hole and extending below the bottom of the contact hole, and wherein the T-shaped portion overlies another interlayer dielectric layer.

A contact structure formed in a peripheral circuit area or a logic circuit area of a semiconductor device including a dynamic random access memory (DRAM) having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area, the contact structure comprising:

• a lower interconnection including a capacitor upper electrode of the plurality of DRAM cells;
• an interlayer dielectric layer formed on the lower interconnection and having a contact hole exposing a region of the lower interconnection;
• and
• an upper interconnection formed on the interlayer dielectric layer, filling the contact hole and being electrically connected to the lower interconnection,
• wherein the lower interconnection has a substantially T-shaped portion in cross section, thee T-shaped portion having a larger width than the bottom of the contact hole and extending below the bottom of the contact hole.

A method of forming a contact structure in a peripheral circuit area or a logic circuit area of a semiconductor device including a dynamic random access memory (DRAM) having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area, the method comprising:

• forming a capacitor upper electrode of each DRAM cell and concurrently forming a lower interconnection of the same material as the capacitor upper electrode to have a T-shape in cross section on a predetermined portion of the peripheral circuit area or the logic circuit area;
• forming an interlayer dielectric layer on the lower interconnection, the interlayer dielectric layer having a contact hole exposing a region of the lower interconnection;
• and
• forming an upper interconnection on the interlayer dielectric layer, the upper interconnection filling the contact hole and electrically connected to the lower interconnection.

A method of forming a plurality of contact structures having contact holes of different depths in a peripheral circuit area or a logic circuit area of a semiconductor device including a dynamic random access memory (DRAM) having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area, the method comprising:

• forming a mold insulation layer on a substrate including a capacitor lower electrode contact plug of each DRAM cell;
• patterning the mold insulation layer, thereby forming a lower electrode opening exposing the capacitor lower electrode contact plug and a lower interconnection opening where a contact structure having a shallow contact hole among the plurality of contact structures is to be formed;
• forming a lower electrode layer by depositing a conductive material on a surface of the mold insulation layer and the openings;
• concurrently forming a cylinder-shaped capacitor lower electrode within the lower electrode opening and a cylinder-shaped dummy lower electrode pattern within the lower interconnection opening by removing the lower electrode layer deposited on the mold insulation layer;
• forming a dielectric layer on the surface of the substrate including the capacitor lower electrode and the dummy lower electrode pattern;
• forming an upper electrode layer filling the cylinder-shaped capacitor lower electrode and the cylinder-shaped dummy lower electrode pattern by depositing a conductive material on the surface of the dielectric layer to a predetermined thickness;
• concurrently forming the capacitor upper electrode of each DRAM cell and a lower interconnection having a T-shape in cross section in the lower interconnection opening by patterning the upper electrode layer;
• forming an interlayer dielectric layer on the surfaces of the upper electrode and the lower interconnection;
• forming a relatively shallow contact hole exposing the lower interconnection and a relatively deep contact hole exposing a predetermined conductive layer below the lower interconnection by etching the interlayer dielectric layer;
• and
• forming upper interconnections on the interlayer dielectric layer, the upper interconnections filling the contact holes and being electrically connected to the lower interconnection and the predetermined conductive layer.