Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

A structure of at least two vertical capacitors inside a spiral inductor for high-frequency and mixed digital and analog applications, comprising:

• a semiconductor substrate, said substrate having been provided with at least one MOS device on the surface thereof, at least two contact junctions having been provided in the surface of said substrate, said at least two contact junctions being contact junctions to which bottom electrodes of at least two vertical capacitors to be created on the surface of said substrate are being connected, a base layer of dielectric having been deposited over the surface of said substrate, including the surface of said at least two contact junctions, at least two conductive contact plugs having been formed through said base layer of dielectric contacting said at least two contact junctions provided in said surface of said substrate, said at least two contact plugs forming contacts for a bottom electrode of overlying at least two capacitors, the surface of said base layer of dielectric having been polished;
• a first etch stop layer deposited over the surface of said base layer of dielectric;
• a first layer of conductive material deposited over the surface of said first etch stop layer;
• a first pattern of interconnect lines formed on the surface of said first etch stop layer, said first pattern of interconnect lines comprising a first layer of coils of said spiral inductor;
• a first layer of dielectric deposited over the surface of said base layer of dielectric, including the surface of said first pattern of interconnect lines;
• a first via created in said first layer of dielectric, said first via being aligned with and contacting said first layer of interconnect lines;
• a second pattern of interconnect lines created on the surface of said first layer of dielectric, said second pattern of interconnect lines comprising a second layer of coils of said spiral inductor;
• a second layer of dielectric deposited over the surface of said first layer of dielectric, including the surface of said second pattern of interconnect lines;
• a second via created in said second layer of dielectric, said second via providing an electrical connection between said second pattern of interconnect lines and an adjacent, overlying pattern of interconnect lines;
• a third pattern of interconnect lines created on the surface of said second layer of dielectric, said third pattern of interconnect lines comprising a third layer of coils of said spiral inductor;
• a third layer of dielectric deposited over the surface of said second layer of dielectric, including the surface of said third pattern of interconnect lines, said third layer of interconnect lines making electrical contact with said second via created in said second layer of dielectric, said third layer of dielectric being an upper layer of dielectric;
• a second etch stop layer deposited over the surface of said third layer of dielectric;
• at least two openings created in said second etch stop layer, said at least two openings being aligned with said at least two conductive contact plugs provided in said base layer of dielectric;
• at least two openings having sidewalls further having bottom surfaces created in said third, second, first layer of dielectric and said first etch stop layer, said at least two openings being surrounded by coils comprising said first, second and third layer of coils of said spiral conductor, said etching partially exposing inner coils of said first, second and third layer of coils of said spiral conductor, continuing said etching to the point of exposing the surface of said at least two conductive contact plugs created in said base layer of dielectric;
• double layered spacers′created on the sidewalls of said openings created in said first, second, third layer of dielectric and said first etch stop layer;
• a layer of Ti/TiN or Ti/TaN conformally deposited over the surface of said double layered spacers on the sidewalls of said at least two openings created in said first, second, third layer of dielectric and said first etch stop layer and over said bottom surfaces of said at least two openings, including the surface of said second etch stop layer, said layer of Ti/TiN or Ti/TaN having been removed from the surface of said second etch stop layer, exposing the surface of said second etch stop layer, further said layer of Ti/TiN or Ti/TaN having been removed from the surface of said double layered spacers around upper perimeters of said at least two openings created in said first, second, third layer of dielectric and said first etch stop layer, partially exposing said double layered spacers, said layer of Ti/TiN or Ti/TaN partially left in place overlying said double layered spacers, said layer of Ti/TiN or Ti/TaN in place overlying said bottom surface of said at least two openings;
• a layer of Ta2O5 deposited over the surface of said second etch stop layer, including said layer of Ti/TiN or Ti/TaN in place overlying said double layered spacers, including the surface of said partially exposed double layered spacers, including said bottom surface of said at least two openings;
• a layer of TiN/Ti or TaN/Ti conformally deposited over the surface of said layer of Ta2O5;
• a first layer of conductive material deposited over the surface of said layer of TiN/Ti or TaN/Ti, filling said at least two openings with said first layer of conductive material, said first layer of conductive material having been removed from above the surface of said second etch stop layer, leaving in place a layer of said first layer of metal having a surface and filling said at least two openings;
• a second layer of conductive material, deposited over the surface of said second etch stop layer and the surface of said first layer of metal filling said at least two openings, said second layer of conductive material having been patterned and etched, creating at least two contact points to said at least two vertical capacitors, said at least two contact points overlying said at least two openings created in said first, second, third layer of dielectric and said first etch stop layer, said second layer of conductive material having been removed from the surface of said second etch stop layer.