Flash memory with less susceptibility to charge gain and charge loss
AssigneeAdvanced Micro Devices, Inc.
InventorsStephen Keetai Park, Jeffrey A. Shields
Life of this patent
Estimating the term…
Abstract
An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or alternately small contact-to-floating gate distance is reduced by a capping layer disposed over a gate stack and a base layer of the flash memory. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The etch characteristics of at least the first and second insulative layer differs from an interlevel dielectric to control the dimensions of a contact extending through the interlevel dielectric and the capping layer to the base layer.
Claims22
An integrated circuit including a plurality of transistors, each of the transistors having a gate stack including a floating gate, the transistors being at least partially covered by a triple layered capping layer and an interlevel dielectric, wherein the triple layered capping layer includes a bottom buffer layer, a middle insulative layer, and a highly transparent layer, wherein a contact extends through the capping layer and the interlevel dielectric between adjacent gate stacks of the plurality of transistors and the configuration of the triple layered capping layer and the contact makes the integrated circuit resistant to charge gain or charge loss associated with the gate stacks, wherein only the bottom buffer layer extends continuously from a level below a top surface of the floating gate conductor to a top surface of the gate stack in a cross-sectional view through the contact and the first gate stack.
An integrated circuit, comprising:
- a first transistor having a first gate stack disposed on a base layer;
- a second transistor having a second gate stack disposed on the base layer, wherein the first and second gate stack each include a floating gate conductor having a first thickness;
- a triple layered capping layer disposed over the first gate stack and the second gate stack, wherein the triple layered capping layer includes a buffer layer, a first insulative layer, and a second insulative layer, at least one layer of the triple layered capping layer extending over a first portion of the base layer between the first gate stack and the second gate stack;
- an interlevel dielectric disposed over the capping layer;
- and
- a contact substantially disposed between the first gate stack and the second gate stack, the contact extending through the interlevel dielectric and the capping layer to be electrically connected to a second portion of the base layer, wherein the contact has a bottom width through the capping layer smaller than a top width through the interlevel dielectric, wherein the first insulative layer and the second insulative layer terminate on a side wall of the contact at a level above the first gate stack.
A method of manufacturing an integrated circuit, comprising:
- providing a gate stack on a base layer, the gate stack includes a floating gate conductor having a first thickness;
- providing a triple layered capping layer having a second thickness greater than the first thickness, the layered capping layer being provided over the gate stack and the base layer, wherein the layered capping layer includes a buffer layer, a first insulative layer, and a second insulative layer;
- providing an interlevel dielectric over the capping layer;
- and
- etching the buffer layer, the first insulative layer, the second insulative layer, and the interlevel dielectric to form a hole extending to the base layer, wherein the hole includes at least one of a width wider at the interlevel dielectric than at the buffer layer and a step-like feature near the base layer, wherein the first insulative layer and the second insulative terminate at a side wall of the contact and the buffer layer extends from a top surface of the base layer to a level above a top surface of the gate stack along the side wall of the contact.
Dependencies are inferred from the claim text.