Semiconductor integrated circuit device having hierarchical test interface circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazutami Arimoto, Hiroki Shimano
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Abstract
A plurality of test interface circuits are disposed in correspondence with a plurality of DRAM cores. An upper test interface circuit transmits a test control signal or the like supplied from the outside to each of or one of the plurality of test interface circuits in accordance with a memory core selection signal. When all of the DRAM cores are designated as targets of an operation test, test output data from the DRAM cores is compared with each other by a data comparing circuit and is outputted as judge flag data reflecting the result of the comparison to the outside.
Claims17
A semiconductor integrated circuit device comprising:
- a plurality of memory circuits operating synchronously with an operation clock signal and executing a given operation instruction;
- a plurality of test interface circuits provided in correspondence with said plurality of memory circuits, each for supplying said operation instruction as well as inputting and outputting test data from and to a corresponding one of said plurality of memory circuits in an operation test;
- and
- an upper test interface circuit capable of performing the supply of said operation instruction and the input and output of said test data based on a test operation instruction given on each of said plurality of test interface circuits in said operation test,
- said upper test interface circuit including a data comparing circuit for judging based on comparison among a plurality of data output from said plurality of test interface circuits.
Dependencies are inferred from the claim text.