Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure

An improved method of fabricating a polycide self-aligned contact structure for MOSFET devices in a SRAM cell on a semiconductor substrate in which the electrical isolation between the contact and the gate structure is improved comprising;

• forming a gate insulator layer on the semiconductor substrate,
• depositing a first polysilicon layer on said gate insulator layer,
• depositing a first metal silicide layer on said first polysilicon layer,
• depositing a first insulator layer on said first metal silicide layer.
• patterning said first insulator layer by a first anisotropic etching,
• dip etching the exposed metal silicide layer in an isotropic etchant for metal silicide to form an undercut in only the top edge of the first metal silicide layer beneath the overlying edge of said first insulator layer,
• continuing the patterning of said first metal silicide layer and said first polysilicon layer by a second anisotropic etching, to form openings that define polycide gate structures on said gate insulator layer,
• ion implanting a first conductivity imparting dopant into said semiconductor substrate through said openings in regions not covered by said polycide gate structures to form lightly doped source and drain regions,
• depositing a second insulator layer on said substrate that extends into said openings formed by the patterning, and into said undercut in said metal silicide layer,
• anisotropically etching said second insulator layer to form sidewall spacers on the sides of said polycide gate structure,
• ion implanting a second conductivity imparting dopant into said semiconductor substrate to form heavily doped source and drain regions,
• depositing a third insulator layer,
• opening a hole in said third insulator layer thereby forming a self-aligned SAC opening and exposing said heavily doped source and drain regions in the space defined by said sidewall spacers,
• depositing a thin second polysilicon layer in contact with said heavily doped source and drain regions and said sidewall spacers,
• depositing a thin second metal silicide layer over said second polysilicon layer,
• patterning said second metal silicide layer and said second polysilicon layer to create a SAC structure.