Method of forming nonvolatile memory device utilizing a hard mask

A method for fabricating a three-dimensional array comprising:

• forming a silicon layer having an upper surface;
• forming a masking layer over the silicon layer;
• patterning the masking layer;
• etching at least the silicon layer in alignment with the patterned masking layer to define memory array features, the features having an upper surface;
• filling between the features with a dielectric material which is softer than the masking layer;
• planarizing the dielectric material with the masking layer acting as a stop;
• removing the patterned masking layer;
• and
• forming an antifuse layer on the upper surface of the features.

A method for fabricating a three-dimensional memory array comprising:

• forming a polysilicon layer;
• forming a masking layer comprising silicon nitride over the polysilicon layer on an upper surface of the polysilicon layer;
• patterning the masking layer;
• etching at least the polysilicon layer in alignment with the patterned masking layer to define parallel, spaced-apart memory lines;
• filling spaces between the memory lines with a dielectric material which planarizes more readily than silicon nitride;
• planarizing the dielectric material with the silicon nitride layer acting as an etchant stop;
• removing the silicon nitride layer;
• forming a silicon dioxide layer over the polysilicon lines.

A method of forming a nonvolatile memory array comprising:

• forming a first stack of films having a top silicon film of a first conductivity type;
• forming a masking layer on said top silicon film of said first stack of films;
• patterning said masking layer to form a patterned masking layer;
• etching said first stack of films in alignment with said patterned masking layer to form a plurality of spaced-apart lines from said first stack of films;
• depositing a dielectric material between said plurality of spaced-apart lines and on said patterned masking layer;
• planarizing said dielectric material with a chemical mechanical polishing process utilizing said masking layer as a polish stop;
• removing said patterned masking layer from said plurality of spaced-apart lines;
• forming an antifuse on said top silicon film of said plurality of spaced-apart lines;
• and
• forming a second stack of films having a lower silicon film of a second conductivity type opposite said first conductivity type on said antifuse on said top silicon film of said first plurality of rail stacks.

A method of forming a memory comprising:

• forming a first stack of films having a top silicon film;
• forming a hard mask layer on said silicon top film;
• patterning said hard mask layer into a patterned hard mask having a plurality of spaced-apart lines;
• etching said first stack of films in alignment with said patterned hard mask to form a plurality of spaced-apart lines from said first stack of films;
• depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said hard mask;
• planarizing said dielectric utilizing said hard mask as a planarization stop;
• removing said hard mask;
• depositing a conductive film over said top silicon film of said plurality of spaced-apart lines and over said planarized dielectric;
• patterning said conductive film into a plurality of conductive lines which run orthogonal to said first plurality of lines formed in said first stack of films;
• and
• etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart first stack of films.

A method of forming a memory comprising:

• forming a first stack of films having a top silicon film;
• forming a conductive hard mask layer on said silicon top film;
• patterning said conductive hard mask into a patterned conductive hard mask having a plurality of spaced-apart lines;
• etching said first stack of films in alignment with said patterned conductive hard mask to form a plurality of spaced-apart lines from said first stack of film;
• depositing a dielectric between said plurality of spaced-apart lines of said first film stack and onto said conductive hard mask;
• planarizing said dielectric utilizing said conductive hard mask as a planarization stop;
• depositing a conductive film over and in direct contact with said patterned conductive hard mask on said plurality of spaced-apart lines;
• patterning said conductive film into a plurality of conductive lines with run orthogonal to said first plurality of lines formed in said first stack of films;
• and
• etching said plurality of spaced-apart lines of said first stack of films in alignment with said conductive lines to form a plurality of pillars from said plurality of spaced-apart lines of said first stack of films.