Low resistance semiconductor process and structures

A process used to manufacture a semiconductor device comprising:

• providing a semiconductor substrate assembly comprising a silicon wafer and at least one dielectric layer formed over said wafer;
• removing a portion of said dielectric layer to form a hole therein to expose said silicon wafer;
• forming a polycrystalline silicon structure within said hole and over said semiconductor substrate assembly wherein said polycrystalline silicon structure contacts said silicon wafer;
• subsequent to forming said polycrystalline silicon structure, removing a portion of said dielectric layer to expose a conductive transistor gate portion;
• forming a blanket layer over said substrate assembly wherein said blanket layer comprises a refractory metal layer over said at least one dielectric layer and further comprises a refractory metal silicide layer which contacts said polycrystalline silicon structure and said conductive transistor gate portion;
• and
• removing said refractory metal layer.

A process used to manufacture a semiconductor device, comprising:

• providing a semiconductor substrate assembly comprising a semiconductor wafer, a plurality of conductive transistor gate portions formed over said wafer, a first dielectric layer overlying said conductive transistor gate portions, and a second dielectric layer overlying said semiconductor wafer;
• removing a portion of said second dielectric layer to form a hole therein and to expose said semiconductor wafer;
• forming a polycrystalline silicon layer in said hole which contacts said semiconductor wafer;
• subsequent to forming said polycrystalline silicon layer, removing a portion of said first dielectric layer to expose said conductive transistor gate portions, wherein said polycrystalline silicon layer and said conductive transistor gate portions are each exposed;
• and
• forming a silicide layer which contacts said conductive transistor gate portions and said polycrystalline silicon layer.

A process for forming a semiconductor device, comprising:

• providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of conductive transistor gate portions each having a TEOS cap thereon and a pair of nitride spacers along each said gate, a plurality of conductive plugs each contacting said wafer, and a BPSG layer overlying said conductive transistor gate portions and contacting said active area;
• etching a portion of said BPSG layer to expose said TEOS caps, wherein a portion of said BPSG layer remains on said active area after completion of said etch;
• removing a portion of said TEOS caps to expose said conductive transistor gate portions;
• and
• forming a titanium silicide layer simultaneously to contact said conductive transistor gate portions and said plugs.

A process for forming a semiconductor device, comprising:

• providing a semiconductor substrate assembly comprising a semiconductor wafer;
• forming a conductive plug over said assembly, said plug having a sidewall and an upper surface which intersects said sidewall;
• and
• forming a layer of silicide which contacts said upper surface and said sidewall of said conductive plug.

A method used during the formation of a semiconductor device, comprising:

• providing a semiconductor substrate assembly comprising a semiconductor wafer having a plurality of polysilicon transistor gates formed thereover, each gate having an associated cap and spacers, said assembly further comprising a planar dielectric layer formed over said gates and over said semiconductor wafer;
• etching said planar dielectric layer to form a plurality of openings therein;
• forming a polysilicon plug layer within said openings;
• planarizing said polysilicon plug layer and said dielectric layer simultaneously;
• subsequent to said planarization of said dielectric layer, removing said dielectric layer to expose a portion of each said cap;
• removing a portion of each said cap to expose said polysilicon transistor gate associated therewith;
• forming a blanket conductive layer to contact said planarized plug layer, each said exposed polysilicon transistor gate, and at least one of said cap and said spacers associated with each said exposed polysilicon transistor gate;
• processing said blanket conductive layer to react said blanket conductive layer with said polysilicon gates and with said polysilicon plug layer, wherein said portion of said conductive layer which contacts said at least one of said cap and said spacers remains unreacted;
• and
• removing said portion of said conductive layer which remains unreacted subsequent to said processing of said blanket conductive layer.