Method for and device having STI using partial etch trench bottom liner

A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of:

• providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate;
• etching the silicon active layer to form an isolation trench wherein an unetched silicon layer remains at bottom of the isolation trench;
• oxidizing exposed silicon on sidewalls of the isolation trench and in the unetched silicon layer at the bottom of the isolation trench so as to electrically isolate from one another portions of the silicon active layer separated by the isolation trench and to round corners on an upper portion of the silicon active layer;
• and
• filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.