Method of making an EEPROM cell with asymmetric thin window

A method of making a scalable nonvolatile memory cell, said method comprising:

• selecting a scale factor limited by the minimum process feature size defined by the manufacturing equipment used to make said memory cell;
• applying said scale factor to a first positive power rail, and applying a larger scale factor to a second positive power rail, said second power rail being about three times greater than said first power rail;
• determining the dimensions of a charge-transfer region based on the value of said second positive power rail, the dimensions of said charge-transfer region being smaller than minimum process feature size defined by the manufacturing equipment used to make said memory cell;
• forming field oxide regions having spaced apart, opposed barrier walls defining the width limits of the active area of said memory cell, said field oxide being formed on a substrate of first conductivity type;
• constructing a first gate oxide within said active area defined by said opposed field oxide barrier walls;
• defining a window region having dimensions equal to said minimum process feature size, said window region being defined to partly encompass said active area and partly encompass only a selected one of said field oxide regions, the part of said window region within said active area being said charge-transfer region and the part of window region within said selected field oxide region being a no-charge-transfer region;
• etching to remove oxide from within said defined window region, the amount of oxide etched away being substantially equal to the thickness of said first gate oxide, whereby said substrate is exposed within said window region;
• growing a tunnel oxide within both of said charge-transfer and no-charge-transfer regions of said window region, said tunnel oxide being at most half as thick as said first gate oxide;
• laying a first polysilicon strip layer over said first gate oxide and extending from one of said field oxide barrier walls to the opposing field oxide barrier wall, said first polysilicon strip partly overlapping both of said opposed field oxide barrier walls, said first polysilicon strip completely covering said charge-transfer region of said window region such that said charge-transfer region does not extend to the boundaries of said first polysilicon strip, the length dimension of said first polysilicon strip layer being orthogonal to said width limits of the active area of said memory cell, the length of said polysilicon strip being the base for said selected scale factor;
• covering said first poly silicon strip layer with a second gate oxide;
• laying a second polysilicon strip layer over said second gate oxide and said first polysilicon strip layer, said second polysilicon strip layer extending beyond both of said field oxide region;
• applying an ion implant step to construct source and drain regions on either side of said first and second polysilicon strip layers, said drain and source regions being distant from said charge-transfer region of said window region.