Field programmable logic arrays with vertical transistors

A method of forming a programmable logic array, the method comprising the steps of:

• forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;
• forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate;
• forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;
• forming a gate dielectric on at least a portion of the side surface of the pillars;
• forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;
• forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars;
• forming an intergate dielectric, interposed between ones of the floating gates and ones of the control lines;
• forming an intergate dielectric, interposed between the two control lines between the common pillars;
• forming a plurality of input lines that interconnect with some of the control lines;
• forming at least one first source and drain interconnection line interconnecting ones of the first source and drain regions;
• forming a plurality of interconnecting array lines that interconnect from the second source and drain regions corresponding to the control lines having connection with the input lines to the control lines not connected to the input lines;
• and
• forming a plurality of output lines, each output line interconnecting with the second source and drain regions not connected to the interconnecting array lines;
• wherein the step of forming the at least one first source and drain interconnection line is carried out at least partially within the substrate.

A method of forming a programmable logic array, the method comprising the steps of:

• forming a plurality of first conductivity type semiconductor pillars upon a substrate, each pillar having top and side surfaces;
• forming a plurality of first source and drain regions, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate;
• forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first source and drain region;
• forming a gate dielectric on at least a portion of the side surface of the pillars;
• forming a plurality of floating gates, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric;
• forming a plurality of control lines, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars;
• forming an intergate dielectric, interposed between ones of the floating gates and ones of the control lines;
• forming an intergate dielectric, interposed between the two control lines between the common pillars;
• forming a plurality of input lines that interconnect with some of the control lines;
• forming at least one first source and drain interconnection line interconnecting ones of the first source and drain regions;
• forming a plurality of interconnecting array lines that interconnect from the second source and drain regions corresponding to the control lines having connection with the input lines to the control lines not connected to the input lines;
• and
• forming a plurality of output lines, each output line interconnecting with the second source and drain regions not connected to the interconnecting array lines;
• wherein the step of forming the plurality of pillars further comprises the steps of:
• growing an epitaxial layer on the substrate;
• etching the epitaxial layer and a portion of the underlying substrate to form a plurality of first troughs therein for carrying an insulator;
• and
• etching the epitaxial layer to form therein a plurality of second troughs, substantially orthogonal to the plurality of first troughs, the second troughs for carrying the input lines.

A method of forming a programmable logic array on a substrate, the method comprising the steps of:

• forming an AND plane and an OR plane, comprising:
• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• and
• forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.

A method of forming a programmable logic array on a substrate, the method comprising the steps of:

• forming an AND plane and an OR plane, comprising:
• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• forming split control line regions between opposing floating gate regions in the second troughs;
• separating from the floating gate regions in the second troughs by the intergate dielectric layer;
• separating the split control lines by the intergate dielectric layer.

A method of forming a programmable logic array on a substrate, the method comprising the steps of:

• forming an AND plane and an OR plane, comprising:
• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• forming control line regions between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer;
• and
• forming an inverter in communication with the AND plane and the OR plane;
• and
• forming a driver in communication with the AND plane and the OR plane.

A method of forming a programmable logic array on a substrate, the method comprising the steps of:

• forming an AND plane and an OR plane, comprising:
• forming a first source and drain layer at a surface of the substrate;
• forming a semiconductor epitaxial layer on the first source and drain layer;
• forming a second source and drain layer at a surface of the epitaxial layer;
• etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
• forming an insulator in the first troughs;
• etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
• forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
• forming a conductive layer in the second troughs;
• removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer;
• forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs;
• forming split control line regions between opposing floating gate regions in the second troughs;
• separating from the floating gate regions in the second troughs by the intergate dielectric layer;
• separating the split control lines by the intergate dielectric layer;
• forming an inverter in communication with the AND plane and the OR plane;
• and
• forming a driver in communication with the AND plane and the OR plane.