Methods for forming memory cell structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYuan-Hung Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Min-Hwa Chi, Chih-Hsing Yu
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Abstract
Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.
Claims12
A method for fabricating a memory cell structure comprising:
- providing a semiconductor substrate;
- forming within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode;
- forming over the field effect transistor (FET) device, and electrically connected with one of the pair of source/drain regions, a capacitor structure having a sidewall;
- forming laterally adjacent the sidewall of the capacitor structure a sacrificial spacer layer;
- forming laterally adjacent the sacrificial spacer layer and further spaced from the sidewall of the capacitor structure a passivating dielectric layer;
- forming through the passivating dielectric layer a bitline stud layer electrically connected with the other of the pair of source/drain regions;
- and
- stripping from adjacent the sidewall of the capacitor structure the sacrificial spacer, such as to provide an air gap void interposed between the capacitor structure and bitline stud layer.
A method for fabricating a memory cell structure comprising:
- providing a semiconductor substrate;
- forming within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode;
- forming over the field effect transistor (FET) device, and electrically connected with one of the pair of source/drain regions, a capacitor structure comprising a blanket capacitor plate layer having an upper topographic portion and a lower topographic portion;
- forming over the blanket capacitor plate layer a variable thickness blanket mask layer having a greater thickness over the upper topographic portion of the blanket capacitor plate layer than the lower topographic portion of the blanket capacitor plate layer;
- and
- etching completely through the variable thickness blanket mask layer and the blanket capacitor plate layer at the lower typographic portions thereof to form a patterned capacitor plate layer having formed thereupon a variable thickness patterned mask layer.
Dependencies are inferred from the claim text.