Semiconductor device and method of manufacturing the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsAkiharu Miyanaga, Nobuo Kubo
Life of this patent
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Abstract
In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain side is restrained by the pining regions 105, a short-channel effect can be restrained effectively. Also, because a passage through which carriers move is ensured, high mobility can be maintained.
Claims48
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film and a gate electrode on a semiconductor substrate;
- adding impurities from an oblique direction with respect to said semiconductor substrate using said gate electrode and masks;
- and
- forming a source region, a drain region and a channel forming region in a self-aligning manner with said gate electrode as a mask;
- wherein impurity regions having a conductive type opposite to that of said source region and said drain region are formed under said gate electrode locally at predetermined intervals along a channel width direction.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film and a gate electrode on a semiconductor substrate;
- adding first impurities having a first conductive type from an oblique direction with respect to said semiconductor substrate using said gate electrode and masks;
- and
- adding second impurities having a second conductivity type in a self-aligning manner with said gate electrode as a mask;
- thereby a source region, a drain region and a channel forming region are defined;
- wherein impurity regions having the first conductive type are formed under said gate electrode at one or several positions at predetermined intervals along a channel width direction.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film and a gate electrode on a semiconductor substrate;
- adding a first impurity having a first conductive type at a first concentration to said semiconductor substrate at an oblique angle with respect to a direction perpendicular to the semiconductor substrate using said gate electrode and masks;
- and
- adding a second impurity having a second conductive type at a second concentration to said semiconductor substrate in a self-aligning manner using said gate electrode as a mask to define impurity regions in a channel forming region;
- wherein impurity regions having the first conductive type are formed under said gate electrode at one or several positions at predetermined intervals along a channel width direction,
- wherein said second concentration is higher than said first concentration.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film and a gate electrode on a semiconductor substrate;
- adding a first impurity to said semiconductor substrate at an oblique angle with respect to a direction perpendicular to the semiconductor substrate using said gate electrode and masks;
- adding a second impurity to said semiconductor substrate in a self-aligning manner using said gate electrode as a mask to define impurity regions in a channel forming region;
- and
- adding said second impurity to semiconductor substrate so as to form source and drain regions in said semiconductor substrate,
- wherein a conductive type of said first impurity is different from a conductivity of said second impurity.
A method according to claim wherein 20, oblique angle is 7 to 83°.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a gate insulating film and a gate electrode on a semiconductor substrate;
- adding a first impurity having a first conductive type at a first concentration to said semiconductor substrate at an oblique angle with respect to a direction perpendicular to the semiconductor substrate using said gate electrode and masks;
- adding a second impurity having a second conductive type at a second concentration to said semiconductor substrate in a self-aligning manner using said gate electrode as a mask to define impurity regions in a channel forming region;
- and
- adding said second impurity having said second conductive type at a third concentration to semiconductor substrate so as to form source and drain regions in said semiconductor substrate,
- wherein impurity regions having the first conductive type are formed under said gate electrode at one or several positions at predetermined intervals along a channel width direction, and
- wherein said third concentration is higher than said second concentration.
Dependencies are inferred from the claim text.