Method for manufacturing thin film transistor panel

A method for manufacturing a thin film transistor panel, the method comprising the steps of:

• forming a gate line with a gate electrode connected to the gate line on an insulating substrate;
• forming a gate insulating layer over the gate line;
• forming an amorphous silicon layer on the gate insulating layer;
• forming an ohmic contact layer on the semiconductor layer;
• forming a photoresist pattern on the ohmic contact layer wherein the photoresist pattern includes a first portion having a first thickness facing an channel region of the TFT, a second portion having a second thickness thicker than the first thickness, and a third portion substantially having no photoresist pattern;
• removing the ohmic contact layer and the semiconductor layer under the third portion of the photoresist pattern;
• removing the first portion of the photoresist pattern to expose the ohmic contact layer;
• removing the ohmic contact layer exposed through the photoresist pattern;
• and
• forming a conductive pattern layer with source and drain electrodes over the patterned semiconductor layer and the gate insulating layer, wherein the drain and source electrodes are separated by the channel region.

A method for manufacturing a thin film transistor panel, the method comprising the steps of:

• forming a gate electrode, a gate insulating layer, a semiconductor layer comprising an ohmic contact layer on an insulating substrate;
• forming a photoresist pattern on the ohmic contact layer wherein the photoresist pattern includes a first portion having a first thickness facing a channel region, a second portion having a second thickness thicker than the first thickness, and a third portion substantially having no photoresist pattern;
• removing the semiconductor layer under the third portion of the photoresist pattern;
• removing the first portion of the photoresist pattern;
• removing the ohmic contact layer underneath the first portion of the photoresist pattern;
• and
• forming a conductive pattern layer with source and drain electrodes over the patterned semiconductor layer and the gate insulating layer, wherein the drain and source electrodes are separated by the channel region.